IP Library › Granted Patent US 8,629,559
Granted Patent B2
US 8,629,559 · App. 13/370,161 · Granted Jan 14, 2014

Stress reduction apparatus with an inverted cup-shaped layer

Inventors: Ying-Ti Lu (Tainan, TW); Wen-Tsao Chen (Tainan, TW); Ming-Ray Mao (Tainan, TW); Kuan-Chi Tsai (Kaohsiung, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 8,629,559
App. No.
13/370,161
Granted
Jan 14, 2014
Kind
B2
Abstract

A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.

Claims (60)

1. An apparatus comprising:

a metal structure formed over a substrate;

an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer; and

an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.

2. The apparatus of claim 1 , wherein the inverted cup shaped stress reduction layer comprises:

a first portion formed on the inter metal dielectric layer, wherein the upper portion of the metal structure is enclosed by the first portion of the inverted cup shaped stress reduction layer; and

a second portion formed on an upper terminal of the metal structure and the first portion of the inverted cup shaped stress reduction layer.

3. The apparatus of claim 2 , wherein the first portion of the inverted cup shaped stress reduction layer has a thickness of about 1000 Å.

4. The apparatus of claim 2 , wherein:

the first portion of the inverted cup shaped stress reduction layer is formed of silicon nitride; and

the second portion of the inverted cup shaped stress reduction layer is formed of silicon nitride.

5. The apparatus of claim 1 , wherein the metal structure is formed of copper.

6. The apparatus of claim 1 , further comprising:

a metal via formed underneath the metal structure.

7. The apparatus of claim 1 , wherein the metal structure is formed by using a single damascene process.

8. A device comprising:

a substrate comprising silicon;

a dielectric layer formed over the substrate;

a first metal layer formed on the dielectric layer;

a first etch stop layer formed over the first metal layer;

a first inter metal dielectric layer formed on the first etch stop layer;

a metal via formed in the first inter metal dielectric layer;

a second etch stop layer formed on the first inter metal dielectric layer;

a second inter metal dielectric layer formed on the second etch stop layer;

a stress reduction layer formed on the second inter metal dielectric layer;

a metal structure having:

a lower portion enclosed by the second etch stop layer;

a middle portion enclosed by the second inter metal dielectric layer; and

an upper portion enclosed by the stress reduction layer; and

a third etch stop layer formed on the stress reduction layer and an upper terminal of the metal structure.

9. The device of claim 8 , further comprising a first metal line formed in the first metal layer.

10. The device of claim 8 , wherein the metal via is electrically coupled to the metal structure.

11. The device of claim 8 , wherein:

the metal structure is formed of copper; and

the metal via is formed of copper.

12. The device of claim 11 , wherein:

the metal structure is formed by using a single damascene process; and

the metal via is formed by using the single damascene process.

13. The device of claim 8 , wherein the stress reduction layer has a thickness of about 1000 Å.

14. The device of claim 8 , wherein the third etch stop layer is formed of a same material as the stress reduction layer.

15. A method comprising:

forming a first inter metal dielectric layer over a substrate;

forming a stress reduction layer on the first inter metal dielectric layer;

forming a second inter metal dielectric layer on the stress reduction layer;

patterning the first inter metal dielectric layer, the stress reduction layer and the second inter metal dielectric layer to form an opening;

filling a metal material into the opening to form a metal structure;

applying a chemical mechanical planarization process to a surface of the second inter metal dielectric layer; and

forming an etch stop layer on the stress reduction layer and an upper terminal of the metal structure.

16. The method of claim 15 , further comprising:

filling the metal material into the opening by using an electrochemical plating process.

17. The method of claim 15 , further comprising:

forming the etch stop layer using a same material as the stress reduction layer.

18. The method of claim 15 , further comprising:

forming a metal via underneath the metal structure, wherein the metal via is electrically coupled to the metal structure.

19. The method of claim 18 , further comprising:

forming the metal via using copper; and

forming the metal structure using copper.

20. The method of claim 19 , further comprising:

forming the metal via using a single damascene process; and

forming the metal structure using the single damascene process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2012
From: LU, YING-TI; CHEN, WEN-TSAO; MAO, MING-RAY; TSAI, KUAN-CHI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 028017/0611 →
Continuity (1)
Related Publication 20130207264A1 · Aug 15, 2013