Reference voltage optimization for flash memory

1. A system comprising:

a reference voltage module configured to generate one or more reference voltages, wherein the one or more reference voltages are usable to determine states of a plurality of memory cells of a nonvolatile memory, and wherein the plurality of memory cells of the nonvolatile memory have a threshold voltage distribution;

a divider module configured to

select, in response to a change in the threshold voltage distribution of the plurality of memory cells, a voltage range within which to update one of the reference voltages, and

divide the voltage range into a plurality of regions;

a counting module configured to count a number of the memory cells having threshold voltages within each of the plurality of regions; and

an update module configured to

select one of the plurality of regions having the threshold voltages of a smallest number of the memory cells, and

update the one of the reference voltages to a voltage value associated with the selected one of the plurality of regions in order to compensate for the change in the threshold voltage distribution of the plurality of memory cells.

2. The system of claim 1 , further comprising:

a voltage generator configured to (i) generate a plurality of voltages corresponding to the plurality of regions and (ii) apply the plurality of voltages to the plurality of memory cells;

a sensing module configured to sense currents through the plurality of memory cells in response to applying each of the plurality of voltages to the plurality of memory cells; and

a threshold voltage module configured to determine the threshold voltages of the plurality of memory cells based on the currents.

3. The system of claim 1 , further comprising a read module configured to read data stored in the plurality of memory cells using the updated one of the reference voltages.

4. The system of claim 1 , wherein the update module is configured to update the one of the reference voltages in response to one or more of:

a number of erase/program cycles performed on the plurality of memory cells;

a number of read errors detected over a period of time while reading the plurality of memory cells; and

a period of time elapsed since a prior updating of the one of the reference voltages.

5. The system of claim 1 , wherein the update module is configured to update the one of the reference voltages independently of others of the one or more reference voltages.

6. The system of claim 1 , wherein the update module is configured to update the one of the reference voltages independently of one or more of (i) data stored in the plurality of memory cells, and (ii) an error correcting code used to store data in the plurality of memory cells.

7. The system of claim 1 , wherein the update module is configured to update the one of the reference voltages by:

keeping others of the one or more reference voltages at respective current values, or

setting others of the one or more reference voltages to predetermined values.

8. The system of claim 1 , wherein in response to (i) each of the plurality of the memory cells storing 3-bits, the one of the reference voltages being one of seven reference voltages, and (ii) Gray mapping being used to map the states of the plurality of memory cells, the system further comprising a selector module configured to select:

a most significant bit (MSB) page comprising MSBs of the plurality of memory cells when the one of the reference voltages being updated is fourth of the seven reference voltages;

a least significant bit (LSB) page comprising LSBs of the plurality of memory cells when the one of the reference voltages being updated is one of first, third, fifth, and seventh of the seven reference voltages; and

a central significant bit (CSB) page comprising CSBs of the plurality of memory cells when the one of the reference voltages being updated is one of second and sixth of the seven reference voltages.

9. A method comprising:

generating one or more reference voltages, wherein the one or more reference voltages are usable to determine states of a plurality of memory cells of a nonvolatile memory, and wherein the plurality of memory cells of the nonvolatile memory have a threshold voltage distribution;

selecting, in response to a change in the threshold voltage distribution of the plurality of memory cells, a voltage range within which to update one of the reference voltages;

dividing the voltage range into a plurality of regions;

counting a number of the memory cells having threshold voltages within each of the plurality of regions;

selecting one of the plurality of regions having the threshold voltages of a smallest number of the memory cells; and

updating the one of the reference voltages to a voltage value associated with the selected one of the plurality of regions in order to compensate for the change in the threshold voltage distribution of the plurality of memory cells.

10. The method of claim 9 , further comprising:

generating a plurality of voltages corresponding to the plurality of regions;

applying the plurality of voltages to the plurality of memory cells;

sensing currents through the plurality of memory cells in response to applying each of the plurality of voltages to the plurality of memory cells; and

determining the threshold voltages of the plurality of memory cells based on the currents.

11. The method of claim 9 , further comprising reading data stored in the plurality of memory cells using the updated one of the reference voltages.

12. The method of claim 9 , further comprising performing the updating in response to one or more of:

a number of erase/program cycles performed on the plurality of memory cells;

a number of read errors detected over a period of time while reading the plurality of memory cells; and

a period of time elapsed since a prior updating of the one of the reference voltages.

13. The method of claim 9 , further comprising updating the one of the reference voltages independently of others of the one or more references voltages.

14. The method of claim 9 , further comprising updating the one of the reference voltages independently of one or more of (i) data stored in the plurality of memory cells, and (ii) an error correcting code used to store data in the plurality of memory cells.

15. The method of claim 9 , further comprising updating the one of the reference voltages by:

keeping others of the one or more references voltages at respective current values, or

setting others of the one or more references voltages to predetermined values.

16. The method of claim 9 , wherein in response to (i) each of the plurality of the memory cells storing 3-bits, the one of the reference voltages being one of seven reference voltages, and (ii) Gray mapping being used to map the states of the plurality of memory cells, the method further comprising:

selecting a most significant bit (MSB) page comprising MSBs of the plurality of memory cells when the one of the reference voltages being updated is fourth of the seven reference voltages;

selecting a least significant bit (LSB) page comprising LSBs of the plurality of memory cells when the one of the reference voltages being updated is one of first, third, fifth, and seventh of the seven reference voltages; and

selecting a central significant bit (CSB) page comprising CSBs of the plurality of memory cells when the one of the reference voltages being updated is one of second and sixth of the seven reference voltages.