Graphene field effect transistor

1. A method of manufacturing a semiconductor structure, comprising:

forming a mandrel comprising an insulator material on an insulator layer on a substrate, wherein the insulator material has angled sidewalls and a top surface;

forming a seed material on the sidewalls and the top surface of the insulator material;

forming a graphene field effect transistor (FET) on the seed material; and

removing the seed material;

forming an upper insulator layer over the graphene FET;

wherein the removing the seed material comprises forming a vent hole in the upper insulator layer;

the vent hole extends completely through a depth of graphene; and

the vent hole extends along an entire length of the graphene across an upper surface of the mandrel, such that the graphene on the mandrel is bisected into discrete sections.

2. The method of claim 1 , wherein the forming the graphene FET comprises forming a graphene layer on the seed material.

3. The method of claim 2 , wherein the forming the graphene FET comprises forming a source electrode and a drain electrode on the graphene layer.

4. The method of claim 3 , wherein the forming the graphene FET comprises forming a gate dielectric on the source electrode, the drain electrode, and the graphene layer.

5. The method of claim 4 , wherein the forming the graphene FET comprises forming a gate electrode on the gate dielectric.

6. The method of claim 2 , wherein the seed material comprises nickel and the forming the graphene layer comprises a chemical vapor deposition on the nickel.

7. The method of claim 2 , further comprising doping the graphene layer with one n-type and p-type doping.

8. The method of claim 1 , wherein the removing the seed material comprises etching the seed material through the vent hole.

9. The method of claim 1 , further comprising plugging the vent hole.

10. The method of claim 1 , wherein the removing the seed material forms an air gap between a graphene layer of the graphene FET and the mandrel.

11. The method of claim 10 , further comprising plugging the vent hole and filling the air gap with an insulator material.

12. The method of claim 1 , further comprising forming the mandrel with a substantially trapezoidal cross-sectional shape having the sidewall and another sidewall.

13. The method of claim 12 , further comprising:

forming the seed material on the other sidewall; and

forming a second graphene FET on the other sidewall.

14. A method of manufacturing a semiconductor structure, comprising:

forming a mandrel on a semiconductor substrate;

forming a sacrificial seed material on first and second sidewalls of the mandrel;

forming a graphene layer on the sacrificial seed material on the first and second sidewalls of the mandrel;

forming source electrodes and drain electrodes on the graphene layer;

forming a gate dielectric on the source electrodes, the drain electrodes, and the graphene layer;

forming gate electrodes on the gate dielectric;

forming an insulator layer over the source electrodes, drain electrodes, and gate electrodes;

forming a vent hole in the insulator layer, the gate electrode, and the graphene; and

removing the sacrificial seed material through the vent hole.

15. The method of claim 14 , wherein the mandrel is composed of an insulator material.

16. The method of claim 14 , wherein the vent hole extends completely through a depth of the graphene.

17. The method of claim 16 , wherein the vent hole extends along an entire length of the graphene across an upper surface of the mandrel, such that the graphene on the mandrel is divided into discrete sections.

18. The method of claim 14 , wherein the removing the sacrificial seed material through the vent hole forms a gap between the graphene and the mandrel, and further comprising filling the gap with an insulator material that is formed between the graphene and the mandrel.

19. The method of claim 14 , wherein the graphene has a first portion arranged at a first angle relative to an upper surface of a substrate, a second portion arranged at a second angle relative to the upper surface of the substrate, and a third portion arranged between the first portion and the second portion, wherein the first angle is different than the second angle.

20. The method of claim 19 , wherein at least one of the source electrodes is on the first portion of the graphene and the third portion of the graphene.

21. The method of claim 4 , further comprising:

forming an upper insulator layer over the graphene FET;

forming an electrical contact contacting the source electrode by: masking the upper insulator layer; etching an opening through the upper insulator layer and the gate dielectric; and filling the opening with an electrically conductive material.

22. A method of manufacturing a semiconductor structure, comprising:

forming an insulator material on an insulator layer on a substrate, wherein the insulator material has angled sidewalls and a top surface;

forming a seed material on the sidewalls and the top surface of the insulator material;

forming a graphene field effect transistor (FET) on the seed material; and

removing the seed material;

wherein the forminc the graphene FET comprises forming a graphene layer on the seed material;

the forming the graphene FET comprises forming a source electrode and a drain electrode on the graphene layer; and

the source electrode and the drain electrode each are formed on and over an angled portion of the graphene layer and a top portion of the graphene layer that is at an angle relative to the angled portion of the graphene layer.