Memory devices having select gates with P type bodies, memory strings having separate source lines and methods
Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.
1. A method for erasing a memory cell string, comprising:
biasing a plurality of memory cell gates to a first voltage, wherein the memory cell gates are adjacent to a n type body region; and
biasing a source line to a second voltage different from the first voltage, wherein biasing the source line biases the n type body region through a p-n junction at a source end of the body region.
2. The method of claim 1 , wherein biasing the plurality of memory cell gates to the first voltage includes biasing the plurality of memory cell gates to approximately zero volts.
3. The method of claim 2 , wherein biasing the source line to the second voltage includes biasing the source line to approximately twenty volts.
4. The method of claim 1 , further comprising floating select gates of the string and floating a data line coupled to the string, wherein biasing the source line couples the select gates and the data line to approximately the first voltage.
5. The method of claim 1 , further comprising biasing select gates of the string to at least the first voltage.
6. The method of claim 1 , further comprising biasing a data line coupled to the string to approximately the first voltage.
7. A method of operating a memory cell in a selected string of memory cells, wherein a selected string is adjacent to a non-selected string, a data line is coupled to both the selected string and the non-selected string, a first source line is coupled to the selected string, and a second source line is coupled to the non-selected string, the method comprising:
biasing a plurality of memory cell gates to a first voltage, wherein the memory cell gates are adjacent to a n type body region;
biasing a source line to a second voltage different from the first voltage, wherein biasing the source line biases the n type body region through a p-n junction at a source end of the body region;
biasing the first source line to a first source voltage;
biasing the data line to a data line voltage;
biasing a drain select gate of the selected string to a drain select gate voltage; and
biasing the second source line to a second source voltage, wherein the second source voltage is higher than the first source voltage.
8. The method of operation of claim 7 , wherein the method includes an erase operation.
9. The method of operation of claim 7 , wherein the method includes a programming operation.
10. The method of operation of claim 7 , wherein the method includes a reading operation.