Reference current generating circuit, reference voltage generating circuit, and temperature detection circuit
View Patent ↗A reference current generating circuit with high current mirror accuracy is provided by low power supply voltage operation. The reference current generating circuit includes a cascode current mirror circuit 1 outputting mirror currents I 1 and I 2 , and a reference current Iref, a current-voltage converter circuit 2 converting the mirror current I 1 into a voltage V 1 , a current-voltage converter circuit 3 converting the mirror current I 2 into a voltage V 2 , a differential amplifier 4 in which the voltage V 1 is input to a first input terminal and the voltage V 2 is input to a second input terminal, a voltage-current converter circuit 5 converting a voltage V 3 output from the differential amplifier 4 into currents I 3 and I 4 , and a current-voltage converter circuit 6 converting the current I 3 into a voltage V 4 which is output to a gate of a transistor in the cascode current mirror circuit.
1. A semiconductor circuit comprising:
a first current-voltage converter circuit comprising a first p-channel transistor; and
a cascode current mirror circuit comprising second to ninth p-channel transistors,
wherein gates of the first to fifth p-channel transistors and a drain of the first p-channel transistor are electrically connected to a third node,
wherein a drain of the second p-channel transistor and gates of the sixth to ninth p-channel transistors are electrically connected to a fourth node,
wherein a drain of the third p-channel transistor is electrically connected to a first node,
wherein a drain of the fourth p-channel transistor is electrically connected to a second node,
wherein a drain of the sixth p-channel transistor is electrically connected to a source of the second p-channel transistor,
wherein a drain of the seventh p-channel transistor is electrically connected to a source of the third p-channel transistor,
wherein a drain of the eighth p-channel transistor is electrically connected to a source of the fourth p-channel transistor,
wherein a drain of the ninth p-channel transistor is electrically connected to a source of the fifth p-channel transistor,
wherein a source of the first p-channel transistor and sources of the sixth to ninth p-channel transistors are electrically connected to a high power supply potential line,
wherein the first node is electrically connected to a first input terminal of a differential amplifier,
wherein the second node is electrically connected to a second input terminal of the differential amplifier,
wherein an output terminal of the differential amplifier is electrically connected to a gate of a tenth transistor and a gate of an eleventh transistor,
wherein a drain of the tenth transistor is electrically connected to the third node, and
wherein a drain of the eleventh transistor is electrically connected to the fourth node.
2. The semiconductor circuit according to claim 1 , wherein a reference current is output from a drain of the fifth p-channel transistor.
3. The semiconductor circuit according to claim 2 , further comprising:
a fourth current-voltage converter circuit converting the reference current into a reference voltage.
4. The semiconductor circuit according to claim 2 , further comprising:
a temperature detection circuit comprising:
a detection circuit detecting temperature using the reference current.
5. A semiconductor circuit comprising:
a first current-voltage converter circuit comprising a first p-channel transistor and a second p-channel transistor; and
a cascode current mirror circuit comprising third to tenth p-channel transistors,
wherein gates of the first to sixth p-channel transistors and a drain of the first p-channel transistor are electrically connected to a third node,
wherein a drain of the second p-channel transistor is electrically connected to a source of the first p-channel transistor,
wherein a drain of the third p-channel transistor and gates of the seventh to tenth p-channel transistors are electrically connected to a fourth node,
wherein a drain of the fourth p-channel transistor is electrically connected to a first node,
wherein a drain of the fifth p-channel transistor is electrically connected to a second node,
wherein a drain of the seventh p-channel transistor is electrically connected to a source of the third p-channel transistor,
wherein a drain of the eighth p-channel transistor is electrically connected to a source of the fourth p-channel transistor,
wherein a drain of the ninth p-channel transistor is electrically connected to a source of the fifth p-channel transistor,
wherein a drain of the tenth p-channel transistor is electrically connected to a source of the sixth p-channel transistor,
wherein a source of the second p-channel transistor and sources of the seventh to tenth p-channel transistors are electrically connected to a high power supply potential line,
wherein the first node is electrically connected to a first input terminal of a differential amplifier,
wherein the second node is electrically connected to a second input terminal of the differential amplifier,
wherein an output terminal of the differential amplifier is electrically connected to a gate of an eleventh transistor and a gate of a twelfth transistor,
wherein a drain of the eleventh transistor is electrically connected to the third node, and
wherein a drain of the twelfth transistor is electrically connected to the fourth node.
6. The semiconductor circuit according to claim 5 , wherein a reference current is output from the drain of the fifth p-channel transistor.
7. The semiconductor circuit according to claim 6 , further comprising:
a second current-voltage converter circuit converting the reference current into a reference voltage.
8. The semiconductor circuit according to claim 6 , further comprising:
a temperature detection circuit comprising:
a detection circuit detecting temperature using the reference current.
9. A semiconductor circuit comprising:
a first current-voltage converter circuit comprising a first p-channel transistor; and
a cascode current mirror circuit comprising second to ninth p-channel transistors,
wherein gates of the first to fifth p-channel transistors and a drain of the first p-channel transistor are electrically connected to a third node,
wherein a drain of the second p-channel transistor and gates of the sixth to ninth p-channel transistors are electrically connected to a fourth node,
wherein a drain of the third p-channel transistor is electrically connected to a first node,
wherein a drain of the fourth p-channel transistor is electrically connected to a second node,
wherein a drain of the sixth p-channel transistor is electrically connected to a source of the second p-channel transistor,
wherein a drain of the seventh p-channel transistor is electrically connected to a source of the third p-channel transistor,
wherein a drain of the eighth p-channel transistor is electrically connected to a source of the fourth p-channel transistor,
wherein a drain of the ninth p-channel transistor is electrically connected to a source of the fifth p-channel transistor,
wherein a source of the first p-channel transistor and sources of the sixth to ninth p-channel transistors are electrically connected to a high power supply potential line,
wherein the first node is electrically connected to a first input terminal of a second current-voltage converter circuit,
wherein the second node is electrically connected to a second input terminal of a third current-voltage converter circuit,
wherein a first output terminal of the second current-voltage converter circuit is electrically connected to a third input terminal of a differential amplifier,
wherein a second output terminal of the third current-voltage converter circuit is electrically connected to a fourth input terminal of the differential amplifier,
wherein a third output terminal of the differential amplifier is electrically connected to a fifth input terminal of a voltage-current converter circuit, and
wherein a fourth output terminal of the voltage-current converter circuit is electrically connected to the third node, and a fifth output terminal of the voltage-current converter circuit is electrically connected to the fourth node.
10. The semiconductor circuit according to claim 9 ,
wherein the second current-voltage converter circuit is configured to receive a first mirror current from the first node of the cascode current mirror circuit and convert the first mirror current into a first voltage,
wherein the third current-voltage converter circuit is configured to receive a second mirror current from the second node of the cascode current mirror circuit and convert the second mirror current into a second voltage,
wherein the first voltage is input to the third input terminal of the differential amplifier and the second voltage is input to the fourth input terminal of the differential amplifier, the first voltage and the second voltage being converted into a third voltage by the differential amplifier,
wherein the voltage-current converter circuit is configured to receive the third voltage and convert the third voltage into a third current to output to the third node, and into a fourth current to output to the fourth node, and
wherein the first current-voltage converter circuit is configured to convert the third current into a fourth voltage to output to the cascode current mirror circuit.
11. The semiconductor circuit according to claim 9 , wherein a reference current is output from a drain of the fifth p-channel transistor.
12. The semiconductor circuit according to claim 11 , further comprising:
a fourth current-voltage converter circuit converting the reference current into a reference voltage.
13. The semiconductor circuit according to claim 11 , further comprising:
a temperature detection circuit comprising:
a detection circuit detecting temperature using the reference current.
14. A semiconductor circuit comprising:
a first current-voltage converter circuit comprising a first p-channel transistor and a second p-channel transistor; and
a cascode current mirror circuit comprising third to tenth p-channel transistors,
wherein gates of the first to sixth p-channel transistors and a drain of the first p-channel transistor are electrically connected to a third node,
wherein a drain of the second p-channel transistor is electrically connected to a source of the first p-channel transistor,
wherein a drain of the third p-channel transistor and gates of the seventh to tenth p-channel transistors are electrically connected to a fourth node,
wherein a drain of the fourth p-channel transistor is electrically connected to a first node,
wherein a drain of the fifth p-channel transistor is electrically connected to a second node,
wherein a drain of the seventh p-channel transistor is electrically connected to a source of the third p-channel transistor,
wherein a drain of the eighth p-channel transistor is electrically connected to a source of the fourth p-channel transistor,
wherein a drain of the ninth p-channel transistor is electrically connected to a source of the fifth p-channel transistor,
wherein a drain of the tenth p-channel transistor is electrically connected to a source of the sixth p-channel transistor, and
wherein a source of the second p-channel transistor and sources of the seventh to tenth p-channel transistors are electrically connected to a high power supply potential line,
wherein the first node is electrically connected to a first input terminal of a second current-voltage converter circuit,
wherein the second node is electrically connected to a second input terminal of a third current-voltage converter circuit,
wherein a first output terminal of the second current-voltage converter circuit is electrically connected to a third input terminal of a differential amplifier,
wherein a second output terminal of the third current-voltage converter circuit is electrically connected to a fourth input terminal of the differential amplifier,
wherein a third output terminal of the differential amplifier is electrically connected to a fifth input terminal of a voltage-current converter circuit, and
wherein a fourth output terminal of the voltage-current converter circuit is electrically connected to the third node, and a fifth output terminal of the voltage-current converter circuit is electrically connected to the fourth node.
15. The semiconductor circuit according to claim 14 ,
wherein the second current-voltage converter circuit is configured to receive a first mirror current from the first node of the cascode current mirror circuit and convert the first mirror current into a first voltage,
wherein the third current-voltage converter circuit is configured to receive a second mirror current from the second node of the cascode current mirror circuit and convert the second mirror current into a second voltage,
wherein the first voltage is input to the third input terminal of the differential amplifier and the second voltage is input to a fourth input terminal of the differential amplifier, the first voltage and the second voltage being converted into a third voltage by the differential amplifier,
wherein the voltage-current converter circuit is configured to receive the third voltage and convert the third voltage into a third current to output to the third node, and into a fourth current to output to the fourth node, and
wherein the first current-voltage converter circuit is configured to convert the third current into a fourth voltage to output to the cascode current mirror circuit.
16. The semiconductor circuit according to claim 14 , wherein a reference current is output from the drain of the fifth p-channel transistor.
17. The semiconductor circuit according to claim 16 , further comprising:
a fourth current-voltage converter circuit converting the reference current into a reference voltage.
18. The semiconductor circuit according to claim 16 , further comprising:
a temperature detection circuit comprising:
a detection circuit detecting temperature using the reference current.