Memory compatibility system and method

1. An apparatus, comprising:

a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard;

a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard;

a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket;

a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system; and

a power regulation module communicatively coupled to the virtualization module and the second socket, the power regulation module configured to output an amount of power to the second socket based upon the initialization data.

2. The apparatus of claim 1 ,

wherein the virtualization module is further configured to transmit the first initialization data to the memory buffer module; and

wherein the memory buffer module is further configured to initialize the memory module inserted into the second socket according to the second standard using the first initialization data.

3. The apparatus of claim 2 , wherein the memory buffer module is configured to perform a timing initialization on the memory module inserted into the second socket according to the second standard using the first initialization data.

4. The apparatus of claim 1 , wherein the second standard is different than the first standard.

5. The apparatus of claim 4 , where in the first standard is the JEDEC DDR4 standard and the second standard is JEDEC DDR3 standard.

6. The apparatus of claim 1 , wherein the first initialization data includes serial presence detect (SPD) data associated with the memory module.

7. The apparatus of claim 1 , wherein the second initialization data is indicative of initialization data associated with a memory module conforming to the first standard.

8. The apparatus of claim 1 ,

including a second connector configured to fit into a third socket in the processing system and communicatively coupled to the power regulation module; and

wherein the power regulation module is further configured to draw the amount of power from the second connector.

9. The apparatus of claim 1 , wherein the memory buffer is further configured to map memory module addresses conforming to the first standard to memory addresses conforming to the second standard.

10. An apparatus, comprising:

a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard;

a second socket configured to accept a first memory module therein, the second socket and the first memory module conforming to a second standard promulgated earlier in time than the first standard;

a virtualization module communicatively coupled to the first connector and the second socket, the virtualization module being configured to retrieve serial presence detect (SPD) data from the first memory module via the second socket, the SPD data being associated with the second standard;

a memory buffer module communicatively coupled to the virtualization module, the first connector, and the second socket, the memory buffer module being configured to receive the SPD data from the virtualization module and initialize the first memory module using the SPD data according to the second standard; and

a power regulation module communicatively coupled to the virtualization module and the second socket, the power regulation module configured to output an amount of power to the second socket based upon the SPD data.

11. The apparatus of claim 10 , wherein the virtualization module is configured to transmit via the first connector virtual SPD data to a basic input/output system (BIOS) on the processing system, the virtual SPD data being indicative of SPD data associated with a virtual memory module conforming to the first standard.

12. The apparatus of claim 10 , wherein the memory buffer module is further configured to receive first command signals associated with the first standard from the processing system, translate the first command signals into second command signals associated with the second standard, and transmit the second command signals to the first memory module.

13. The apparatus of claim 10 ,

including a third socket communicatively coupled to the memory buffer module and virtualization module and configured to accept a second memory module therein, the third socket and second memory module conforming to the second standard; and

wherein the virtualization module is further configured to transmit virtual SPD data to the processing system, the virtual SPD data including a virtual capacity value approximately equal to a first capacity value of the first memory module plus a second capacity value of the second memory module.

14. A method, comprising:

retrieving, using a virtualization module, first initialization data from a memory module inserted into a first socket, the memory module and first socket conforming to a first standard;

regulating, using a power regulation module communicatively coupled to the virtualization module, an amount of power provided to the first socket, the regulating being based upon the initialization data;

initializing, using a memory buffer module communicatively coupled to the virtualization module, the memory module according to the first standard, the initializing being based upon the initialization data; and

transmitting, using the virtualization module, second initialization data based upon the first initialization data and associated with a second standard to a processing system through a first connector inserted into a second socket in the processing system, the first connector and second socket conforming to the second standard.

15. The method of claim 14 , including:

receiving, with the memory buffer module, signals associated with the second standard from the processing system through the first connector;

translating, with the memory buffer module, the signals associated with the second standard into signals associated with the first standard; and

transmitting, with the memory buffer module, the signals associated with the first standard to the memory module.

16. The method of claim 15 , wherein the translating includes mapping memory module addresses conforming to the first standard to memory module addresses conforming to the second standard.

17. The method of claim 14 , wherein the second standard is different than the first standard.

18. The method of claim 14 , where in the first standard is the JEDEC DDR4 standard and the second standard is JEDEC DDR3 standard.

19. The method of claim 14 , wherein the retrieving includes retrieving serial presence detect (SPD) data associated with the memory module.

20. The method of claim 14 ,

wherein the transmitting the second initialization data includes configuring the second initialization data to be indicative of initialization data associated with a memory module conforming to the first standard; and

wherein the transmitting includes transmitting the second initialization data to a BIOS on the processing system.