IP Library Granted Patent US 8,642,402
Granted Patent B2
US 8,642,402 · App. 12/526,304 · Granted Feb 4, 2014

Thin film transistor manufacturing method, thin film transistor, thin film transistor substrate and image display apparatus, image display apparatus and semiconductor device

Inventors: Koki Yano (Chiba, JP); Kazuyoshi Inoue (Chiba, JP); Futoshi Utsuno (Chiba, JP); Masashi Kasami (Chiba, JP)
Assignee: Idemitsu Kosan Co., Ltd.
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Quick Facts
Patent No.
US 8,642,402
App. No.
12/526,304
Granted
Feb 4, 2014
Kind
B2
Abstract

To provide a method for producing a thin film transistor improved in stability, uniformity, reproducibility, heat resistance, durability or the like, a thin film transistor, a thin film transistor substrate, an image display apparatus, an image display apparatus and a semiconductor device. In the semiconductor device, a crystalline oxide is used as an N-type transistor and the electron carrier concentration of the crystalline oxide is less than 2×10 17 /cm 3 . Furthermore, the crystalline oxide is a polycrystalline oxide containing In and one or more positive divalent elements selected from Zn, Mg, Cu, Ni, Co and Ca, and the atomic ratio In [In] and the positive divalent element [X][X]/([X]+[In]) is 0.0001 to 0.13.

Claims (41)

1. A method for producing a thin film transistor comprising the steps of: a film-forming step in which an amorphous oxide film is formed as a channel layer; a patterning step in which said amorphous oxide film is patterned by etching; and a crystallization step in which said amorphous oxide film which is patterned in the patterning step is crystallized, resulting in the amorphous oxide film being converted to a crystalline oxide semiconductor film,

wherein said crystallized crystalline oxide semiconductor film is provides a channel layer;

said crystalline oxide semiconductor film contains In and a positive divalent element;

said positive divalent element is one or more elements selected from Zn, Mg, Cu, Co, Ni and Ca; and

an atomic ratio of the In [In] and the positive divalent element [X] by the formula [X]/([X]+[In]) is such that 0.0001≦[X]/([X]+[In])≦0.5.

2. The method for producing a thin film transistor according to claim 1 , wherein said atomic ratio is such that 0.01≦[X]/([X]+[In])≦0.1.

3. The method for producing a thin film transistor according to claim 1 , wherein any one film forming method selected from a sputtering method, a vapor deposition method, an ion plating method, a CVD method, a spray method and a dipping method is used in said film-forming step.

4. The method for producing a thin film transistor according to claim 1 , wherein a sputtering method is used in the film-forming step and said sputtering method is any one selected from a DC magnetron sputtering method, an AC magnetron sputtering method and an RF magnetron sputtering method.

5. The method for producing a thin film transistor according to claim 4 , wherein water or hydrogen is contained in an atmospheric gas in said sputtering method.

6. The method for producing a thin film transistor according to claim 1 , wherein wet etching is used in said patterning step.

7. A method for producing a thin film transistor according to claim 6 , wherein said wet etching is performed by using an etching solution containing one or more acids selected from oxalic acid, hydrochloric acid and phosphoric acid.

8. The method for producing a thin film transistor according to claim 1 , wherein, in said crystallization step, said amorphous oxide film is crystallized according to one or more methods selected from a heat treatment, a plasma treatment and a laser irradiation treatment.

9. The method for producing a thin film transistor according to claim 1 , wherein said crystalline oxide film is subjected to an oxidization step in said crystallization step or after said crystallization treatment.

10. The method for producing a thin film transistor according to claim 9 , wherein said oxidization treatment is performed by one or more treatment methods selected from a heat treatment in the presence of oxygen, an ozone treatment and a plasma treatment.

11. The method for producing a thin film transistor according to claim 1 , wherein a sputtering method is used in the film-forming step to form said amorphous oxide at a temperature lower than 150° C., patterning is performed in said patterning step with an etching solution containing oxalic acid, and a heat treatment is performed in the presence of oxygen at a temperature of 150 to 500° C. in said crystallization step.

12. The method for producing a thin film transistor according to claim 11 , wherein water or hydrogen is contained in an atmospheric gas in said sputtering method.

13. A method for producing a thin film transistor according to claim 1 , wherein a thin film is formed on said crystalline oxide film after said crystallization step, and said thin film is patterned by wet etching.

14. A method for producing a thin film transistor according to claim 13 , wherein said wet etching is performed by using an etching solution containing one or more acids selected from oxalic acid, hydrochloric acid and phosphoric acid.

15. A thin film transistor which is produced by the method for producing a thin film transistor according to claim 1 .

16. A thin film transistor substrate comprising a plurality of thin film transistors according to claim 15 arranged on a substrate or a sheet-like base.

17. An image display apparatus which comprises a thin film transistor according to claim 15 .

18. An active matrix type image display apparatus provided with a light control element and a field-effect type transistor for driving said light control element,

wherein an active layer of said field-effect type transistor is a crystalline oxide semiconductor and the electron carrier concentration of said active layer is less than 2×10 17 /cm 3 ,

said crystalline semiconductor oxide is a polycrystalline oxide containing In and one or more positive divalent elements selected from Zn, Mg, Cu, Ni, Co and Ca; and

an atomic ratio of said In [In] and said positive divalent element [X] by the formula [X]/([X]+[In]) is 0.0001 to 0.13.

19. The image display apparatus according to claim 18 , wherein said crystalline oxide has resistance to PAN.

20. The image display apparatus according to claim 18 , wherein the electron mobility relative to the electron carrier concentration of said crystalline oxide logarithmically proportionally increases in a predetermined range with an increase in said electron carrier concentration.

21. The image display apparatus according to claim 18 , wherein the concentration of Li and Na in said crystalline oxide are 1000 ppm or less.

22. The image display apparatus according to claim 18 , wherein said light control element is a liquid crystal element or an electroluminescence element.

23. A semiconductor device comprising a crystalline oxide as an N-type semiconductor, wherein the electron carrier concentration of said crystalline oxide is less than 2×10 17 /cm 3 ,

wherein said crystalline oxide N-type semiconductor is a polycrystalline oxide containing In and one or more positive divalent element selected from Zn, Mg, Cu, Ni, Co and Ca; and

an atomic ratio of said In [In] and said positive divalent element [X] by the formula [X]/([X]+[In]) is 0.0001 to 0.13.

24. The semiconductor device according to claim 23 , wherein the electron mobility relative to the electron carrier concentration of said crystalline oxide logarithmically proportionally increases by at least changing the atomic ratio of said In [In] and said positive divalent element [X].

25. The semiconductor device according to claim 23 , wherein said crystalline oxide has resistance to PAN.

26. The semiconductor device according to claim 23 , wherein the concentration of Li and Na is 1000 ppm or less.

27. The semiconductor device according to claim 23 , wherein said semiconductor device is a thin film transistor and said crystalline oxide is used as a channel layer.

28. The semiconductor device according to claim 23 , wherein said semiconductor device is provided with a P-type region and an N-type region and said crystalline oxide is used in said N-type region.

29. The semiconductor device according to claim 28 , wherein said semiconductor device is a PN junction type transistor.

30. The semiconductor device according to claim 23 , wherein said semiconductor device is a static induction transistor, a Schottky barrier transistor, a Schottky diode or a resistive element, and said crystalline oxide is used as an electron conductor.

31. The semiconductor device according to claim 23 , wherein said semiconductor device is an integrated circuit and contains an N-type thin film transistor using said crystalline oxide.

32. The semiconductor device according to claim 23 , wherein said semiconductor device is provided with a first region composed of said crystalline oxide and a second region forming a hetero junction for said first region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2010
From: YANO, KOKI; INOUE, KAZUYOSHI; UTSUNO, FUTOSHI; KASAMI, MASASHI
To: IDEMITSU KOSAN CO., LTD.
Reel/Frame 025313/0109 →
Priority Claims (3)
JP 2007-030591 · Feb 9, 2007 · national
JP 2007-032546 · Feb 13, 2007 · national
JP 2007-038392 · Feb 19, 2007 · national
Continuity (1)
Related Publication 20110050733A1 · Mar 3, 2011