Method of manufacturing strained source/drain structures
A method includes forming a gate structure over a semiconductor substrate. The gate structure defines a channel region in the semiconductor substrate. Trenches are formed in the semiconductor substrate, and the trenches are interposed by the channel region. A first semiconductor layer is epitaxially grown in the trenches, and the first semiconductor layer has a first dopant with a first dopant concentration. A second semiconductor layer is epitaxially grown over the first semiconductor layer, and the second semiconductor layer has a second dopant with a second dopant concentration. The second dopant has an electrical carrier type opposite to an electrical carrier type of the first dopant.
1. A method comprising:
forming a gate structure over a semiconductor substrate, the gate structure defining a channel region in the semiconductor substrate;
forming trenches in the semiconductor substrate, interposed by the channel region;
epitaxially growing a first semiconductor layer in the trenches, the first semiconductor layer having a first dopant with a first dopant concentration; and
epitaxially growing a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a second dopant with a second dopant concentration, wherein the second dopant has an electrical carrier type opposite to an electrical carrier type of the first dopant.
2. The method of claim 1 , further comprising:
forming spacers adjoining opposite sidewalls of the gate structure.
3. The method of claim 1 , wherein the first dopant concentration ranges from about 1E18 atoms/cm 3 to about 5E19 atoms/cm 3 .
4. The method of claim 1 , wherein the second dopant concentration ranges from about 5E19 atoms/cm 3 to about 5E21 atoms/cm 3 .
5. The method of claim 1 , wherein the epitaxially growing the first semiconductor layer is performed by epitaxially growing SiGe, and the first dopant is phosphorous or arsenic.
6. The method of claim 1 , wherein the epitaxially growing the second semiconductor layer is performed by epitaxially growing SiGe, and the second dopant is boron or BF 2 .
7. The method of claim 1 , wherein the epitaxially growing the first semiconductor layer is performed by epitaxially growing Si or SiC, and the first dopant is boron or BF 2 .
8. The method of claim 1 , wherein the epitaxially growing the second semiconductor layer is performed by epitaxially growing Si or SiC, and the second dopant is phosphorous or arsenic.
9. The method of claim 1 , wherein the second dopant concentration is set to be higher than the first dopant concentration.
10. A method comprising:
forming a trench in a semiconductor substrate, the trench being adjacent to a channel region;
forming a first structure in the trench, the first structure being in contact with a bottom surface and sidewalls of the trench, and the first structure having a first dopant with a first dopant concentration; and
forming a second structure over the first structure and at least partially in the trench, the second structure having a second dopant with a second dopant concentration, and the second dopant having an electrical carrier type opposite to an electrical carrier type of the first dopant.
11. The method of claim 10 , wherein the first dopant concentration ranges from about 1E18 atoms/cm 3 to about 5E19 atoms/cm 3 .
12. The method of claim 10 , wherein the second dopant concentration ranges from about 5E19 atoms/cm 3 to about 5E21 atoms/cm 3 .
13. The method of claim 10 , wherein the forming the first structure is performed by epitaxially growing SiGe, and the first dopant is phosphorous or arsenic.
14. The method of claim 10 , wherein the forming the second structure is performed by epitaxially growing SiGe, and the second dopant is boron or BF 2 .
15. The method of claim 10 , wherein the forming the first structure is performed by epitaxially growing Si or SiC, and the first dopant is boron or BF 2 .
16. The method of claim 10 , wherein the forming the second structure is performed by epitaxially growing Si or SiC, and the second dopant is phosphorous or arsenic.
17. The method of claim 10 , wherein the second dopant concentration is set to be higher than the first dopant concentration.
18. A method comprising:
forming a gate structure over a substrate, the gate structure defining a channel region in the substrate;
forming two trenches in the substrate, the two trenches being interposed by the channel region, and sidewalls and the bottom portions of the two trenches being along one or more {111} facets of the substrate;
epitaxially growing a first structure in the trenches, the first structure extending along the sidewalls and bottom portions of the two trenches, and the first structure having a first dopant with a first dopant concentration; and
epitaxially growing a second structure over the first structure, the second structure having a second dopant with a second dopant concentration, the second dopant having an electrical carrier type opposite to an electrical carrier type of the first dopant.
19. The method of claim 18 , wherein the first dopant concentration ranges from about 1E18 atoms/cm 3 to about 5E19 atoms/cm 3 .
20. The method of claim 18 , wherein the second dopant concentration ranges from about 5E19 atoms/cm 3 to about 5E21 atoms/cm 3 .