IP Library › Granted Patent US 8,642,457
Granted Patent B2
US 8,642,457 · App. 13/039,315 · Granted Feb 4, 2014

Method of fabricating semiconductor device

Inventors: Ssu-I Fu (Kaohsiung, TW); I-Ming Tseng (Kaohsiung, TW); En-Chiuan Liou (Tainan, TW); Shih-Hung Tsai (Tainan, TW)
Assignee: United Microelectronics Corp.
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Quick Facts
Patent No.
US 8,642,457
App. No.
13/039,315
Granted
Feb 4, 2014
Kind
B2
Abstract

The present invention provides a method of fabricating a semiconductor device. A substrate is provided. A first region and a second region are defined on the substrate. A first interfacial layer, a sacrifice layer and a sacrifice gate layer are disposed on the first region. The sacrifice layer and the sacrifice gate layer are disposed on the second region of the substrate. Next, a first etching step is performed to remove the sacrifice gate layer in the first region and the second region. Then, a second etching step is performed to remove the sacrifice layer in the first region and the second region to expose the substrate of the second region. Lastly, a second interfacial layer is formed on the substrate of the second region.

Claims (28)

1. A method of fabricating a semiconductor device, comprising:

providing a substrate, wherein a first region and a second region are defined on the substrate, a first interfacial layer, a sacrifice layer and a sacrifice gate layer are disposed in sequence on the substrate of the first region, the sacrifice layer and the sacrifice gate layer are disposed in sequence on the substrate of the second region;

performing a first etching process to remove the sacrifice gate in the first region and the second region;

performing a second etching process to remove the sacrifice layer in the first region and the second region to expose the substrate only in the second region; and

forming a second interfacial layer on the substrate in the second region.

2. The method of fabricating a semiconductor device according to claim 1 , wherein the sacrifice layer has an etching selectivity substantially greater than 10:1 with respect to the sacrifice gate layer, the first interfacial layer and the substrate.

3. The method of fabricating a semiconductor device according to claim 1 , wherein a first spacer is disposed on a sidewall of the first interfacial layer, the sacrifice layer and the sacrifice gate in the first region, and a second spacer is disposed on a sidewall of the sacrifice layer and the sacrifice gate in the second region, wherein the sacrifice layer has an etching selectivity substantially greater than 4:1 with respect to the first spacer and the second spacer.

4. The method of fabricating a semiconductor device according to claim 3 , wherein the first spacer and the second spacer comprise SiN.

5. The method of fabricating a semiconductor device according to claim 1 , wherein the sacrifice layer comprises a high-k material.

6. The method of fabricating a semiconductor device according to claim 5 , wherein the high-k material comprises hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO), strontium bismuth tantalite (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT) or barium strontium titanate (Ba x Sr 1-x TiO 3 , BST).

7. The method of fabricating a semiconductor device according to claim 5 , wherein the second etching process comprises using an etchant comprising HF and HCl.

8. The method of fabricating a semiconductor device according to claim 1 , wherein the sacrifice layer comprises TiN or TaN.

9. The method of fabricating a semiconductor device according to claim 8 , wherein the second etching process comprises using an etchant comprising NH 4 OH, H 2 O 2 and H 2 O.

10. The method of fabricating a semiconductor device according to claim 1 , wherein the sacrifice layer comprises SiN.

11. The method of fabricating a semiconductor device according to claim 10 , wherein the second etching process comprises using an etchant comprising H 3 PO 4 .

12. The method of fabricating a semiconductor device according to claim 1 , wherein the substrate comprises a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate or a silicon-on-insulator (SOI).

13. The method of fabricating a semiconductor device according to claim 1 , wherein the first interfacial layer comprises SiO 2 .

14. The method of fabricating a semiconductor device according to claim 1 , wherein the sacrifice gate layer comprises poly-silicon.

15. The method of fabricating a semiconductor device according to claim 1 , wherein the sacrifice layer is used as an etching stop layer during the first etching process.

16. The method of fabricating a semiconductor device according to claim 1 , wherein after the second etching process, the first interfacial layer is still disposed on the substrate in the first region.

17. The method of fabricating a semiconductor device according to claim 1 , wherein the second interfacial layer comprises SiO 2 .

18. The method of fabricating a semiconductor device according to claim 1 , wherein the step of forming the second interfacial layer comprises a thermal oxidation process.

19. The method of fabricating a semiconductor device according to claim 1 , further comprising forming a high-k layer and a metal layer on the first interfacial layer in the first region and the second interfacial layer in the second region.

20. A method of fabricating a semiconductor device, comprising:

providing a substrate, wherein a first region and a second region are defined on the substrate, a first interfacial layer, a sacrifice layer and a sacrifice gate layer are disposed in sequence on the substrate of the first region, the sacrifice layer and the sacrifice gate layer are disposed in sequence on the substrate of the second region;

performing a first etching process to remove the sacrifice gate in the first region and the second region;

performing a second etching process to completely remove the sacrifice layer in the first region and the second region to expose the substrate in the second region, wherein the substrate of the first region is not exposed; and

forming a second interfacial layer on the substrate in the second region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2011
From: FU, SSU-I; TSENG, I-MING; LIOU, EN-CHIUAN; TSAI, SHIH-HUNG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 025891/0348 →
Continuity (1)
Related Publication 20120225545A1 · Sep 6, 2012