Semiconductor device
A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.
1. A semiconductor device, comprising:
a first insulating layer;
a contact plug formed in the first insulating layer;
a first etch stop layer over the first insulating layer;
a second etch stop layer over the first etch stop layer;
a second insulating layer over the second etch stop layer and having a contact opening over the contact plug;
a capacitor disposed in the contact opening and over the contact plug, the capacitor including:
a top electrode;
a bottom electrode; and
a dielectric disposed between the top electrode and the bottom electrode;
wherein the second etch stop layer is removed in the contact opening; and
wherein the first etch stop layer remains in the contact opening.
2. A semiconductor device according to claim 1 , wherein the bottom electrode covers the entire contact opening.
3. A semiconductor device according to claim 1 , wherein the bottom electrode directly contacts the contact plug and portions of the first etch stop layer in the contact opening.
4. A semiconductor device according to claim 1 , wherein the top electrode and the bottom electrode comprise metal.
5. A semiconductor device according to claim 1 , further comprising another contact plug formed over and electrically connected to the contact plug.
6. A semiconductor device according to claim 1 , further comprising a silicide layer underlying the contact plug, the contact plug engaging the silicide layer.
7. A semiconductor device according to claim 1 , further comprising a semiconductor substrate and an embedded memory cell formed on the semiconductor substrate, the memory cell including the capacitor.
8. A semiconductor device, comprising:
a first insulating layer;
a contact plug formed in the first insulating layer;
a first etch stop layer over the first insulating layer;
a second etch stop layer over the first etch stop layer;
a second insulating layer over the second etch stop layer and having a contact opening over the contact plug;
a capacitor disposed in the contact opening and over the contact plug, the capacitor including:
a top electrode;
a bottom electrode; and
a dielectric disposed between the top electrode and the bottom electrode;
wherein the bottom electrode directly contacts the contact plug and portions of the first etch stop layer in the contact opening.
9. A semiconductor device according to claim 8 , wherein the bottom electrode covers an entire inner surface of the contact opening.
10. A semiconductor device according to claim 8 , wherein the top electrode and the bottom electrode comprise metal.
11. A semiconductor device according to claim 8 , further comprising another contact plug formed over and electrically connected to the contact plug.
12. A semiconductor device according to claim 8 , further comprising a silicide layer underlying the contact plug, the contact plug engaging the silicide layer.
13. A semiconductor device according to claim 8 , further comprising a semiconductor substrate and an embedded memory cell formed on the semiconductor substrate, the memory cell including the capacitor.
14. A semiconductor device, comprising:
a first insulating layer;
a contact plug formed in the first insulating layer;
an etch stop layer over the first insulating layer;
a second insulating layer over the etch stop layer and having a contact opening over the contact plug, the contact opening further extending into a partial thickness of the etch stop layer;
a capacitor disposed in the contact opening and over the contact plug, the capacitor including:
a top electrode;
a bottom electrode; and
a dielectric disposed between the top electrode and the bottom electrode;
wherein an upper portion of the contact plug is exposed from the etch stop layer; and
wherein the bottom electrode is in electrical contact with the exposed upper portion of the contact plug, and is free of direct contact with the first insulating layer.
15. A semiconductor device according to claim 14 , wherein the bottom electrode covers an entire inner surface of the contact opening.
16. A semiconductor device according to claim 14 , wherein the bottom electrode directly contacts portions of the etch stop layer in the contact opening.
17. A semiconductor device according to claim 14 , further comprising a semiconductor substrate and an embedded memory cell formed on the semiconductor substrate, the memory cell including the capacitor.
18. A semiconductor device according to claim 17 , wherein the memory cell further comprises a transistor having a doped feature in contact with a lower portion of the contact plug.
19. A semiconductor device according to claim 18 , wherein
the contact plug further comprises a sidewall extending downward from the upper portion to the lower portion of the contact plug; and
the bottom electrode of the capacitor is free of direct contact with the sidewall of the contact plug.
20. A semiconductor device according to claim 14 , further comprising:
a further etch stop layer over the second insulating layer; and
a third insulating layer over the further etch stop layer;
wherein the contact opening extends through the third insulating layer, the further etch stop layer, and the second insulating layer.