Integrated circuit package with discrete components surface mounted on exposed side
An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive back side. Conductive vias extend through the integrated circuit between the front and back sides. A redistribution layer on the back side of the host integrated circuit provides conductive traces and contact pads. The traces of the redistribution layer establish connection between the conductive vias and the contact pads. At least one additional component is surface-mounted on the back side of the host integrated circuit by electrical connection to the contact pads of the redistribution layer to provide a compact three-dimensional structure. In an alternative embodiment, the additional components can be mounted on the active side.
1. An integrated circuit package comprising:
a host integrated circuit having an active front side and an inactive back side, one of said front and back sides being surface-mounted on an underlying support selected from the group consisting of a printed circuit board and an underlying integrated circuit, and the other of said front and back sides providing an exposed side;
conductive vias extending through the host integrated circuit between the front and back sides thereof;
a first redistribution layer on the exposed side of the host integrated circuit providing conductive traces and contact pads; and
a plurality of discrete components, each of said discrete components being surface-mounted on the exposed side of the host integrated circuit by electrical connection to the contact pads of the redistribution layer; and
said conductive traces of the first redistribution layer establishing connection between the conductive vias and the contact pads and providing interconnects interconnecting said discrete components.
2. An integrated circuit package as claimed in claim 1 , wherein the front side of the host integrated circuit is surface-mounted on the underlying support.
3. An integrated circuit package as claimed in claim 1 , wherein the underlying support is formed by one or more additional integrated circuits arranged such that the integrated circuits form a stack with the topmost integrated circuit of the stack forming the host integrated circuit and the bottommost integrated circuit surface-mounted on a printed circuit board.
4. An integrated circuit package as claimed in claim 1 , wherein the first redistribution layer includes a sub passivation layer and a patterned conductive sublayer forming the traces and conductive pads.
5. An integrated circuit package as claimed in claim 1 , wherein the discrete components are surface-mounted by solder connections to the contact pads forming part of the first redistribution layer.
6. An integrated circuit package as claimed in claim 1 , wherein the host integrated circuit has a silicon substrate and the vias are through-silicon-vias.
7. An integrated circuit package as claimed in claim 2 , further comprising a second redistribution layer on the front side of the host integrated circuit, and wherein said second redistribution layer provides interconnection between conductive traces on the front side of the host integrated circuit and contact pads on the underlying support.
8. An integrated circuit package as claimed in claim 1 , wherein the discrete components are embedded in a plastic molding on the exposed side of the host integrated circuit.
9. A method of making an integrated circuit package, comprising: surface mounting one of an active front side and an inactive back side of a host integrated circuit on an underlying support selected from the group consisting of a printed circuit board and an underlying integrated circuit, the other of said active front side and inactive back side providing an exposed side;
forming conductive vias through the host integrated circuit between the front and back side thereof;
forming a first redistribution layer on the exposed side to provide conductive traces and contact pads, the conductive traces being electrically connected to the conductive vias;
surface mounting each of a plurality of discrete components on the exposed side by electrical connection to the contact pads of the first redistribution layer, said conductive traces of the first redistribution layer establishing connection between the conductive vias and the contact pads and providing interconnects interconnecting said discrete components.
10. A method as claimed in claim 9 , wherein the front side of the host integrated circuit is surface mounted on the underlying support.
11. A method as claimed in claim 9 , wherein the front side of the host integrated circuit is surface mounted directly onto a printed circuit board.
12. A method as claimed in claim 10 , wherein the front side of the host integrated circuit is surface mounted onto another integrated circuit so as to form a stack of integrated circuits, which in turn are surface mounted on a printed circuit board.
13. A method as claimed in claim 9 , wherein after forming the first redistribution layer, solder balls are placed onto the contact pads, the discrete components are positioned on the exposed side of the host integrated circuit, and the solder balls are then subjected to a reflow process to secure the discrete components.
14. A method as claimed in claim 9 , wherein the host integrated circuit has a silicon substrate, and the vias are formed as through-silicon vias.
15. A method as claimed in claim 10 , further comprising providing a second redistribution layer on the front side of the host integrated circuit, and wherein said second redistribution layer provides interconnection between conductive traces on the front side and contact pads on the underlying support.
16. A method as claimed in claim 9 , further comprising the step of forming a plastic molding around the discrete components.