Cable redundancy and failover for multi-lane PCI express IO interconnections
Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.
1. A method for providing a failover operation for a connection between a first Peripheral Component Interconnect Express (PCIE) bridge and a first input/output (IO) device, the method comprising:
exchanging a first set of bussed bits between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge;
in response to detecting a failure in the first link, exchanging a second set of bussed bits between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device, wherein the first and the second PCIE bridges are housed in a same PCIE root complex.
2. The method of claim 1 , wherein exchanging the second set of bussed bits in response to detecting the failure comprises:
at a PCIE bridge end, performing a first switch between the first set of lanes and a second set of lanes of the second PCIE bridge for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device using the unused portion of the second link, wherein the unused portion comprises the second set of lanes.
3. The method of claim 2 , wherein exchanging the second set of bussed bits in response to detecting the failure further comprises:
at an IO device end, performing a second switch between the first and the second sets of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device using the unused portion of the second link.
4. The method of claim 3 , further comprising:
in response to detecting the failure in the first link, configuring the second PCIE bridge to stop using the second set of lanes.
5. The method of claim 4 , further comprising:
in response to detecting the failure in the first link, configuring the first PCIE bridge to stop using lanes other than the first set of lanes.
6. The method of claim 1 , wherein each of the first and the second PCIE bridges comprise a PCIE host bridge (PHB).
7. The method of claim 1 , wherein each of the first and the second IO devices comprise a PCIE switch.