IP Library Granted Patent US 8,648,389
Granted Patent B2
US 8,648,389 · App. 13/489,667 · Granted Feb 11, 2014

Semiconductor device with spacer layer between carrier traveling layer and carrier supplying layer

Inventor: Isao Makabe (Yokohama, JP)
Assignee: Sumitomo Electric Industries, Ltd.
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Quick Facts
Patent No.
US 8,648,389
App. No.
13/489,667
Granted
Feb 11, 2014
Kind
B2
Abstract

A nitride semiconductor device is disclosed. The device includes a stack of semiconductor layers including the channel layer, the spacer layer, and the doped layer. The spacer layer is made of AlN while the doped layer is InAlN. A feature of the embodiment is that the spacer layer has a thickness of 0.5 to 1.25 nm.

Claims (19)

1. A semiconductor device, comprising:

a substrate;

a channel layer made of GaN and formed on the substrate,;

a spacer layer made of AlN and formed in the channel layer, the spacer layer forming a two-dimensional electron gas (2DEG) in the channel layer at the interface to the spacer layer; and

a doped layer made of InAlN and formed on the spacer layer, the doped layer having a composition of indium (In) greater than, or equal to 12% and less than, or equal to 18%,

wherein the spacer layer has a thickness greater than, or equal to 0.5 nm and thinner than, or equal to 0.8 nm, and

wherein the doped layer has a Haze index less than 50 ppm, and the 2DEG has sheet resistance less than 300 Ω/□.

2. The semiconductor device of claim 1 ,

further including a topmost layer formed on the doped layer, the topmost layer including gallium nitride (GaN).

3. The semiconductor device of claim 1 ,

further including a gate electrode, a source electrode, and a drain electrode, each being formed on the doped layer,

wherein the source electrode and the drain electrode put the gate electrode therebetween.

4. The semiconductor device of claim 3 ,

further including a cap layer made of GaN and formed on the doped layer,

wherein the gate, source, and drain electrodes are provided on the cap layer.

5. The semiconductor device of claim 4 ,

further including an insulating layer for covering the cap layer exposed between gate, source, and drain electrodes.

6. The semiconductor device of claim 1 ,

wherein the substrate is made of one of silicon carbide (SiC), silicon (Si), GaN, sapphire, and gallium oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2012
From: MAKABE, ISAO
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 028568/0300 →
Priority Claims (2)
JP 2011-128650 · Jun 8, 2011 · national
JP 2011-159229 · Jul 20, 2011 · national
Continuity (1)
Related Publication 20120313145A1 · Dec 13, 2012