Techniques for multi-wire encoding with an embedded clock
Techniques for multi-wire encoding with an embedded clock are disclosed. In one particular exemplary embodiment, the techniques may be realized as a transmitter component. The transmitter component may comprise at least one encoder module to generate a set of symbols, each symbol being represented by a combination of signal levels on a set of wires. The transmitter component may also comprise at least one signaling module to transmit one or more of the symbols over the set of wires according to a transmit clock. The transmitter component may additionally comprise control logic to restrict transmission of first and second subsets of the set of symbols to respective first and second portions of a clock cycle of the transmit clock, such that a signal differential among at least two of the set of wires exhibits a switching behavior that has a same frequency as the transmit clock.
1. A system for multi-wire encoding with an embedded clock, the system comprising:
a first transmitter component, a first receiver component, and a first set of wires coupling the first transmitter component to the first receiver component;
the first transmitter component being configured to:
encode a first set of symbols by representing each symbol with a combination of signal levels transmitted on the first set of wires, and
restrict the transmission of a first subset of the encoded symbols to a first portion of a clock cycle of a transmit clock and to restrict the transmission of a second subset of the encoded symbols to a second portion of the clock cycle of the transmit clock so as to embed a clock signal therein, the clock signal having a same frequency as the transmit clock; and
the first receiver component being configured to:
perform comparisons among the signal levels of the first set of wires, each comparison involving at least two wires,
generate a receive clock from the embedded clock signal based on at least one of the comparisons, the receive clock having the same frequency as the transmit clock, and
decode, under timing control of the receive clock, the encoded symbols based on the comparisons;
a second transmitter component, a second receiver component, and a second set of wires coupling the second transmitter component to the second receiver component;
the second transmitter component being configured to encode a second set of symbols by representing each symbol with a combination of signal levels transmitted on the second set of wires; and
the second receiver component being configured to receive and decode the second set of encoded symbols under timing control of the receive clock;
wherein the transmission of the first set and the second set of wires are grouped to reduce inter-symbol interference among the first set and the second set of encoded symbols.
2. The system of claim 1 , wherein each encoded symbol of the first set of symbols is represented by a respective combination of signal levels on at least three of the set of wires.
3. The system of claim 2 , wherein each encoded symbol of the first subset of the encoded symbols corresponds to a respective one of a plurality of possible bit patterns of a set of input symbols and each encoded symbol of the second subset of the encoded symbols corresponds to a respective one of the plurality of possible bit patterns of the set of input symbols.
4. The system of claim 2 , wherein a total output current on the first set of wires is substantially independent of the encoded symbols being transmitted on the wires during respective time periods.
5. The system of claim 2 , wherein the signal levels are generated based on a two-level pulse amplitude modulation (2-PAM).
6. The system of claim 1 , wherein the first transmitter comprises first and second encoders that are enabled to encode the first set of the encoded symbols, the first encoder outputting encoded symbols from the first subset of the encoded symbols and the second encoder outputting encoded symbols from the second subset of the encoded symbols.
7. The system of claim 1 , wherein:
encoded symbols from the first subset of the encoded symbols are transmitted on respective rising edges of the transmit clock; and
encoded symbols from the second subset of the encoded symbols are transmitted on respective falling edges of the transmit clock.
8. The system of claim 1 , wherein the first subset of the encoded symbols includes three encoded symbols, the second subset of the encoded symbols includes three encoded symbols, and the set of wires includes four wires.
9. The system of claim 1 , wherein the first subset of the encoded symbols includes three encoded symbols, the second subset of the encoded symbols includes three encoded symbols, and the set of wires includes three wires.
10. The system of claim 1 , wherein the first set of wires comprise traces disposed on a printed circuit board.
11. The system of claim 1 , wherein signal levels representative of the encoded symbols are generated based on a three-level pulse amplitude modulation (3-PAM).
12. The system of claim 1 , wherein each of the sequence of encoded symbols has a first number of data bits and each of a sequence of input symbols has a second number of data bits, the first number being at least one more than the second number.
13. The system of claim 1 , wherein the first transmitter component communicates with a memory device over the first set of wires.
14. The system of claim 1 , further comprising:
multiple pairs of the first transmitter component and the first receiver component, wherein, in each pair, the first transmitter component is part of a physical interface of a memory controller and the first receiver component is associated with a micro-buffer of at least one memory module within a memory device that is coupled to the memory controller.