Integrating transistors with different poly-silicon heights on the same die
A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.
1. A method of fabricating an integrated circuit, the method comprising:
depositing a first poly-silicon layer over a first region and a second region, wherein the first region and the second region each have different poly silicon gate structures;
depositing, within the second region, an oxide layer over the first poly-silicon layer;
depositing a second poly-silicon layer over the first poly-silicon layer and the oxide layer;
stripping away a portion of the second poly-silicon layer that lies over the oxide layer such that another portion of the second poly-silicon layer remains after the portion is stripped away;
after the stripping, etching the first and the second poly-silicon layer within the first region to provide at least one first poly-silicon gate region;
after the stripping, etching the first poly-silicon layer within the second region to provide at least one second poly-silicon gate region;
fabricating at least one first poly-silicon figer from the first poly-silicon layer; and
fabricating at least one second poly-silicon finger from the second poly-silicon layer, wherein the at least one first and the at least one second poly-silicon fingers are oriented in a substantially orthogonal manner.
2. The method of claim 1 , wherein the oxide layer has a thickness of about 50-200 angstroms.
3. The method of claim 1 , wherein the first and the second poly-silicon layer each have a thickness of about 500-1000 angstroms.
4. The method of claim 1 , wherein the at least one first poly-silicon gate region includes at least one Flash memory cell, wherein the at least one Flash memory cell includes at least one Flash memory transistor.
5. The method of china 4 , wherein the at least one second poly-silicon gate region includes at least one complex logic device, wherein the at least one complex logic device includes at least one low-voltage transistor.
6. The method of claim 5 , wherein the at least one complex logic device comprises a microprocessor.
7. The method of claim 5 , wherein the at least one Flash memory cell and the at least one complex logic device are embedded within the integrated circuit.
8. The method of claim 5 , wherein the at least one low-voltage transistor comprises a short-channel transistor device.
9. The method of claim 1 , wherein the at least one first poly-silicon gate region further includes at least one high-voltage transistor.
10. A tangible machine-readable storage medium including an electronic design file that is arranged to control the performance of the method of claim 1 .
11. A method of fabricating an integrated circuit, the method comprising:
depositing a first poly-silicon layer over a first region and a second region, wherein the first region and the second region have different poly silicon gate structures;
depositing, within the second region, an oxide layer over the first poly-silicon layer;
depositing a second poly-silicon layer over the first poly-silicon layer and the oxide layer;
stripping away a portion of the second poly-silicon layer that lies over the oxide layer;
etching, within the first region, the first and the second poly-silicon layer to provide at least one first poly-silicon gate region;
etching, within the second region, the first poly-silicon layer to provide at least one second poly-silicon gate region, wherein the at least one first poly-silicon gate region includes at least one Flash memory cell, wherein the at least one Flash memory cell includes at least one Flash memory transistor; and
providing the at least one Flash memory transistor by:
fabricating at least one first poly-silicon finger from the first poly-silicon layer; and
fabricating at least one second poly-silicon finger from the second poly-silicon layer, wherein the at least one first and the at least one second poly-silicon finger are oriented in a substantially orthogonal manner.
12. The method of claim 11 , wherein providing the at least one Flash memory transistor further includes:
depositing an oxide between at least one of the at least one first poly-silicon finger and another adjacent at least one of the at least one first poly-silicon finger.
13. The method of claim 12 , wherein fabricating the at least one second poly-silicon finger further includes:
fabricating the at least one second poly-silicon finger over the at least one first poly-silicon finger and the oxide.
14. A method for fabricating a flash memory device, comprising:
depositing a first poly-silicon layer over a core memory region, a high-voltage region, and a low-voltage region, wherein the core memory region, the high-voltage region, and the low-voltage region, are all located on a single die;
depositing, within the low-voltage region, an oxide layer over the first poly-silicon layer;
depositing a second poly-silicon layer over the first poly-silicon layer and the oxide layer;
stripping away a portion of the second poly-silicon layer that lies over the oxide layer leaving a second portion of the second poly-silicon layer over the core memory region and the high-voltage region;
after the stripping, etching, within the core memory region, the first poly-silicon layer and the second poly-silicon layer to provide at least one Flash memory cell, wherein the at least one Flash memory cell includes at least one Flash memory transistor;
after the stripping, etching, within the high-voltage region, the first poly-silicon layer and the second poly-silicon layer to provide at least one high-voltage transistor;
after the stripping, etching, within the low-voltage region, the first poly-silicon layer to provide at least one low-voltage transistor;
fabricating at least one first poly-silicon finger from the first poly-silicon layer; and
fabricating at least one second poly-silicon finger from the second poly-silicon layer, wherein the at least one first and the at least one second poly-silicon fingers are oriented in a substantially orthogonal manner.
15. A method of fabricating an integrated circuit, the method comprising:
depositing a first poly-silicon layer over a first region and a second region, wherein the first region and the second region have different poly silicon gate structures;
depositing, within the second region, an oxide layer over the first poly-silicon layer, wherein the oxide layer is an oxide-nitride-oxide (ONO) layer;
depositing a second poly-silicon layer over the first polysilicon layer and the oxide layer;
stripping away a portion of the second poly-silicon layer that lies over the oxide layer;
after the stripping, etching the first and the second poly-silicon layer within the first region to provide at least one first poly-silicon gate region;
after the stripping, etching the first poly-silicon layer within the second region to provide at least one second poly-silicon gate region;
fabricating at least one first poly-silicon finger from the first poly-silicon layer; and
fabricating at least one second poly-silicon finger from the second poly-silicon layer, wherein the at least one first and the at least one second poly-silicon fingers are oriented in a substantially orthogonal manner.