Semiconductor devices employing high-K dielectric layers as a gate insulating layer and methods of fabricating the same

1. A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate having a first region and a second region;

forming a nitrogen-containing lower gate insulating layer on the semiconductor substrate;

forming an upper gate insulating layer on the nitrogen-containing lower gate insulating layer;

forming a lower metal layer on the upper gate insulating layer; and

selectively removing the lower metal layer in the first region to form a lower metal layer pattern in the second region,

wherein the upper gate insulating layer in the first region prevents the nitrogen-containing lower gate insulating layer in the first region from being etched during removing of the lower metal layer in the first region the upper gate insulating layer in the first region being partially etched during removing of the lower metal layer in the first region such that at least a portion of the upper gate insulating layer remains on the nitrogen-containing lower gate insulating layer in the first region after the lower metal layer in the first region has been selectively removed.

2. The method as claimed in claim 1 , wherein the first region and the second region are an N-channel MOS transistor region and a P-channel MOS transistor region, respectively.

3. The method as claimed in claim 1 , wherein the forming of the nitrogen-containing lower gate insulating layer includes:

forming a lower high-k dielectric layer on the semiconductor substrate; and

nitrifying the lower high-k dielectric layer.

4. The method as claimed in claim 1 , wherein the forming of the upper gate insulating layer includes forming an upper high-k dielectric layer on the nitrogen-containing lower gate insulating layer, the upper high-k dielectric layer being a metal oxide layer or a metal silicate layer, and applying at least one of a nitrification process and an annealing process to the upper high-k dielectric layer.

5. The method as claimed in claim 4 , wherein:

the nitrification process is applied to the upper high-k dielectric layer to form the upper gate insulating layer, and

after the nitrification process is applied, the upper gate insulating layer has a nitrogen concentration that is lower than that of the nitrogen-containing lower gate insulating layer.

6. The method as claimed in claim 1 , wherein the lower metal layer is formed by sequentially stacking a first titanium nitride layer, an aluminum layer and a second titanium nitride layer.

7. The method as claimed in claim 1 , further comprising forming an upper metal layer on the semiconductor substrate after forming the lower metal layer pattern.

8. The method as claimed in claim 1 , further comprising:

forming a lanthanum-containing material layer on the semiconductor substrate after forming the lower metal layer pattern, and

forming an upper metal layer on the semiconductor substrate after forming the lower metal layer pattern.

9. A method of fabricating a semiconductor device, the method comprising:

forming a nitrogen-containing lower gate insulating layer on a semiconductor substrate having a first region and a second region;

forming an upper gate insulating layer on the nitrogen-containing lower gate insulating layer;

forming a lower metal layer on the upper gate insulating layer; and

selectively removing the lower metal layer in the first region to form a lower metal layer pattern in the second region and partially removing the upper gate insulating layer to form a residue layer in the first region and in upper gate insulating layer pattern in the second region.

10. The method as claimed in claim 9 , further including:

forming a lanthanum-containing material layer and an upper metal layer on the semiconductor substrate,

forming a hard mask layer on the upper metal layer, and

performing annealing such that lanthanum atoms in the lanthanum-containing material layer diffuse toward an interface between the semiconductor substrate and the nitrogen-containing lower gate insulating layer.

11. The method as claimed in claim 10 , further including:

after the annealing, removing the hard mask layer, the upper metal layer, the lower metal layer pattern and the lanthanum-containing material layer to expose the residue layer and the upper gate insulating layer pattern, and

forming a gate metal layer on the residue layer and the upper gate insulating layer pattern.