Nonvolatile memory device including a channel pad having a channel extending portion and a spacer and method of manufacturing the same
A nonvolatile memory device having a vertical structure and a method of manufacturing the same, the nonvolatile memory device including a channel region that vertically extends from a substrate; gate electrodes on the substrate, the gate electrodes being disposed along an outer side wall of the channel region and spaced apart from one another; and a channel pad that extends from one side of the channel region to an outside of the channel region, the channel pad covering a top surface of the channel region.
1. A nonvolatile memory device having a vertical structure, the nonvolatile memory device comprising:
a channel region that vertically extends from a substrate;
gate electrodes on the substrate, the gate electrodes being disposed along an outer side wall of the channel region and spaced apart from one another; and
a channel pad that extends from one side of the channel region to an outside of the channel region, the channel pad covering a top surface of the channel region,
wherein the channel pad includes:
a channel extending portion vertically extending on the channel region, and
a spacer on an outer circumferential surface of the channel extending portion.
2. The nonvolatile memory device as claimed in claim 1 , wherein the spacer forms a bent portion at a boundary with an outer side wall of the channel extending portion or the channel region.
3. The nonvolatile memory device as claimed in claim 1 , wherein an area of a top surface of the channel pad is greater than an area of the top surface of the channel region.
4. The nonvolatile memory device as claimed in claim 1 , further comprising a bit line contact plug on the channel pad, the bit line contact plug being connected to a bit line.
5. The nonvolatile memory device as claimed in claim 1 , further comprising an insulating spacer on a side surface of the channel pad.
6. The nonvolatile memory device as claimed in claim 1 , wherein the channel pad includes:
a cover portion on the channel extending portion, the cover portion having an area greater than an area of the channel extending portion.
7. The nonvolatile memory device as claimed in claim 1 , further comprising a buried insulating layer at a center of the channel region, wherein the channel pad further includes a conductive layer on a top surface of the buried insulating layer, the conductive layer filling in the channel extending portion.
8. The nonvolatile memory device as claimed in claim 7 , wherein a distance between the substrate and a bottom surface of the conductive layer is less than a distance between the substrate and a bottom surface of the spacer.
9. A nonvolatile memory device having a vertical structure, the nonvolatile memory device comprising:
a channel region that vertically extends from a substrate;
gate electrodes on the substrate, the gate electrodes being disposed along an outer side wall of the channel region and spaced apart from one another; and
a conductive channel pad on and electrically connected to the channel region,
wherein:
the channel pad covers a top surface of the channel region,
an area of a top surface of the channel pad is greater than an area of a top surface of the channel region, and
the channel pad includes a conductive channel extending portion overlying the channel region, a conductive layer encompassed by the channel extending portion, and a conductive spacer on an outer circumferential surface of the channel extending portion.
10. The nonvolatile memory device as claimed in claim 9 , further comprising an insulating spacer on an outer circumferential surface of the channel pad.
11. The nonvolatile memory device as claimed in claim 9 , wherein the channel pad further includes a conductive cover portion overlying the channel extending portion and the conductive layer, an area of a top surface of the cover portion being greater than an area of top surfaces of the channel extending portion and the conductive layer.
12. The nonvolatile memory device as claimed in claim 9 , further comprising a bit line contact plug on and electrically connected to the channel pad, the bit line contact plug being electrically connected to a bit line.