Layout for multiple-Fin SRAM cell

1. A device comprising:

a first fin active region, a second fin active region, and a third fin active region extending from a semiconductor substrate, wherein the first and second fin active regions are spaced apart from each other a first distance and the second and third fin active regions are spaced apart from each other a second distance, wherein the second distance is different than the first distance;

a plurality of fin field-effect transistors (FinFETs) formed on at least one of the first, second, and third fin active regions;

a first contact disposed on the first and second fin active regions; and

a second contact disposed on the third fin active region.

2. The device of claim 1 , further comprising a fourth fin active region extending from the semiconductor substrate, the third and fourth fin active regions are spaced way from each other the second distance.

3. The device of claim 1 , wherein the second distance is greater than the first distance.

4. The device of claim 1 , wherein at least one of the first and second fin active regions includes an epitaxy feature formed thereon.

5. The device of claim 4 , wherein the epitaxy feature includes at least one of silicon germanium and silicon carbide.

6. The device of claim 1 , wherein the first contact physically contacts the first and second fin active regions.

7. The device of claim 1 , wherein the plurality of FinFETs include:

a first inverter including a first pull-up transistor (PU- 1 ) and a first and second pull-down transistors (PD- 1 and PD- 2 ); and

a second inverter including a second pull-up transistor (PU- 2 ) and a third and fourth pull-down transistors (PD- 3 and PD- 4 ), the second inverter being cross-coupled with the first inverter for data storage, and

wherein the PD- 1 and PD- 2 are formed on the first and second fin active regions, respectively.

8. A device comprising:

a first fin active region, a second fin active region, and a third fin active region extending from a semiconductor substrate;

a first isolation element extending a first distance from the first fin active region to the second fin active region;

a second isolation element extending a second distance from the second fin active region to the third fin active region, wherein the second distance is different than the first distance;

a plurality of fin field-effect transistors (FinFETs) formed on at least one of the first, second, and third fin active regions;

a first contact disposed on the first and second fin active regions; and

a second contact disposed on the third fin active region.

9. The device of claim 8 , wherein the first and second fin active regions have a first silicon epitaxy feature and a second silicon epitaxy feature, respectively.

10. The device of claim 9 , further comprising a silicide feature formed on the first and second silicon epitaxy features.

11. The device of claim 8 , further comprising a fourth fin active region extending from the semiconductor substrate; and

a third isolation element extending the second distance from the third fin active region to the fourth fin active region.

12. The device of claim 11 , wherein the second contact is not electrically coupled to the fourth fin active region.

13. The device of claim 8 , wherein the plurality of FinFETs includes:

a first pull-up device and a second pull-up device;

a first pull-down device configured with the first pull-up device to form a first inverter;

a second pull-down device configured with the second pull-up device to form a second inverter; and

a first and second pass-gate devices configured with the first and second inverters as a first port.