Redundancy system for non-volatile memory
A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.
1. A redundancy method for a non-volatile memory, comprising:
a) storing program data in register cells;
b) detecting a mismatch between a permanent logic state of a defective cell and a logic state of a bit of program data of the register cells by comparing a logic state of each of the memory cells to a corresponding bit of the program data by each of the register cells and providing a local flag if a mismatch is detected;
c) controlling each of the register cells to execute an inversion operation for providing inverted program data when the mismatch is detected;
d) programming the inverted program data to memory cells of the non-volatile memory; and
e) programming an inversion status cell corresponding to the memory cells if the mismatch is detected.
2. The redundancy method of claim 1 , wherein the permanent logic state of the defective cell mismatches the bit of the program data when the permanent logic state corresponds to a programmed state and the bit inhibits programming of the cell.
3. The redundancy method of claim 1 , wherein one of the register cells is an inversion status register cell, and detecting includes generating a program inversion signal by the inversion status register cell if the permanent logic state of the defective cell mismatches the bit of the program data.
4. The redundancy method of claim 3 , wherein controlling includes inverting the program data at each of the register cells and the inversion status register cell in response to the program inversion signal.
5. The redundancy method of claim 1 , wherein detecting further includes generating a global flag at a last register cell by combining the local flags of each of the register cells with each other.
6. The redundancy method of claim 5 , wherein the last register cell is an inversion status register cell, and detecting includes generating a program inversion signal by the inversion status register cell.
7. The redundancy method of claim 6 , wherein controlling includes inverting the program data at each of the register cells and the inversion status register cell in response to the program inversion signal.
8. The redundancy method of claim 1 , wherein the defective cell is one of the memory cells for storing the input data.
9. The redundancy method of claim 1 , wherein the defective cell is one of the memory cells for storing the inversion status data.
10. The redundancy method of claim 1 , further including executing a read operation after the inverted program data and the inversion status cell have been programmed.
11. The redundancy method of claim 10 , wherein the read operation includes reading data from the memory cells.
12. The redundancy method of claim 11 , wherein the data includes read data and inversion status data.
13. The redundancy method of claim 12 , wherein reading includes storing an inverted version of the read data in the register cells in response to detection of the inversion status data having a logic level indicating the memory cells store an inverted version of the read data.
14. The redundancy method of claim 13 , wherein storing includes inverting the read data prior to storing in the register cells.
15. A redundancy method for a non-volatile memory, comprising:
a) storing program data in register cells, the program data including input data received by the non-volatile memory and inversion status data;
b) detecting a mismatch between a permanent logic state of a defective cell and a logic state of a bit of program data of the register cells;
c) controlling each of the register cells to execute an inversion operation for providing inverted program data when the mismatch is detected;
d) programming the inverted program data to memory cells of the non-volatile memory; and
e) programming an inversion status cell corresponding to the memory cells if the mismatch is detected.
16. The redundancy method of claim 15 , wherein the permanent logic state of the defective cell mismatches the bit of the program data when the permanent logic state corresponds to a programmed state and the bit inhibits programming of the cell.
17. The redundancy method of claim 15 , wherein detecting includes comparing a logic state of each of the memory cells to a corresponding bit of the program data by each of the register cells and wherein comparing includes providing a local flag if a mismatch is detected.
18. The redundancy method of claim 17 , wherein detecting further includes generating a global flag at a last register cell by combining the local flags of each of the register cells with each other.
19. The redundancy method of claim 18 , wherein the last register cell is an inversion status register cell, and detecting includes generating a program inversion signal by the inversion status register cell.
20. The redundancy method of claim 19 , wherein controlling includes inverting the program data at each of the register cells and the inversion status register cell in response to the program inversion signal.