Multi-level LDPC layer decoder
Various embodiments of the present invention provide methods and apparatuses for multi-level layer decoding of non-binary LDPC codes. For example, an apparatus is disclosed for layer decoding of multi-level low density parity check encoded data. The apparatus includes a low density parity check decoder operable to perform layered decoding of a plurality of circulant submatrices from an H matrix. The apparatus also includes a parity check calculator connected to the low density parity check decoder, operable to detect whether a stopping criterion has been met in the low density parity check decoder. The low density parity check decoder is also operable to end a decoding operation at less than a maximum number of iterations when the stopping criterion is met.
1. An apparatus for layer decoding of multi-level low density parity check encoded data comprising:
a low density parity check decoder operable to perform layered decoding of a plurality of circulant submatrices from an H matrix; and
a parity check calculator connected to the low density parity check decoder, operable to detect whether a stopping criterion has been met in the low density parity check decoder, the low density parity check decoder being operable to end a decoding operation at less than a maximum number of iterations when the stopping criterion is met.
2. The apparatus of claim 1 , wherein the stopping criterion is met when H· {circumflex over (ν)} =0 over GF(q), where {circumflex over (ν)} εGE (q) N , with {circumflex over (ν)} comprising an output of the low density parity check decoder, and where H comprises the H matrix and GF(q) comprises a Galois Field associated with the low density parity check decoder.
3. The apparatus of claim 1 , further comprising a controller connected to the low density parity check decoder and to the parity check calculator, the controller being operable to control iterations in the low density parity check decoder and to cause the low density parity check decoder to end the decoding operation when the stopping criterion is met.
4. The apparatus of claim 1 , wherein the parity check calculator comprises a barrel shifter connected to an input of the parity check calculator, the barrel shifter being operable to shift the input from column order to row order.
5. The apparatus of claim 4 , wherein the parity check calculator further comprises a permutation circuit connected to the barrel shifter and operable to arrange non-zero elements in each circulant of the H matrix according to a parity check equation implemented by the parity check calculator.
6. The apparatus of claim 5 , wherein the parity check calculator further comprises a parity check calculation circuit connected to the barrel shifter and operable to implement the parity check equation, wherein the parity check equation comprises H· {circumflex over (ν)} over GF(q), where {circumflex over (ν)} εGF(q) N , with {circumflex over (ν)} comprising an output of the low density parity check decoder, and where H comprises the H matrix and GF(q) comprises a Galois Field associated with the low density parity check decoder.
7. The apparatus of claim 6 , wherein the parity check calculator further comprises a parity register connected to the parity check calculation circuit.
8. The apparatus of claim 7 , wherein the parity check calculator further comprises a multi-stage adder connected to the parity register and operable to add a plurality of parity check results from the parity register to yield an unsatisfied check number and a convergence status.
9. The apparatus of claim 1 , wherein the parity check calculator is operable to process a plurality of inputs in parallel, with an input for each H matrix column having a non-zero entry.
10. The apparatus of claim 1 , wherein the parity check calculator is operable to process a plurality of circulants in parallel.
11. The apparatus of claim 1 , wherein the low density parity check decoder is operable to process values from a current layer and from a connected layer.
12. The apparatus of claim 1 , wherein the low density parity check decoder is operable to calculate R values by identifying a minimum, a next minimum and an index of the minimum for soft log-likelihood-ratio values.
13. The apparatus of claim 1 , wherein the low density parity check decoder and the parity check calculator are implemented as an integrated circuit.
14. The apparatus of claim 1 , wherein the apparatus is incorporated in a storage device.
15. The apparatus of claim 14 , wherein the storage device comprises:
a storage medium maintaining a data set; and
a read/write head assembly operable to sense the data set on the storage medium and to provide an analog output corresponding to the data set, wherein the low density parity check decoder is operable to receive a signal derived from the analog output.
16. The apparatus of claim 1 , wherein the apparatus is incorporated in a data transmission device.
17. A method of manufacturing a multi-level low density parity check layer decoder, comprising:
providing a low density parity check decoder operable to iteratively decode a plurality of circulant submatrices from an H matrix in layered fashion;
providing a parity check calculator connected to a soft log-likelihood-ratio output from the low density parity check decoder; and
providing a controller connected to the low density parity check decoder and to the parity check calculator, wherein the controller is operable to end a decoding operation in the low density parity check decoder when the parity check calculator detects a stopping criterion.
18. The method of claim 17 , wherein the parity check calculator is operable to process a subset of a plurality of layers processed by the low density parity check decoder, wherein the subset of the plurality of layers includes all hard decisions of columns in the H matrix for a low density parity check code associated with the low density parity check decoder.
19. The method of claim 17 , wherein the low density parity check decoder is operable to process non-binary log-likelihood-ratio values.
20. An apparatus for decoding of non-binary multi-level low density parity check encoded data, comprising:
a low density parity check decoder operable to perform layered decoding of a plurality of circulant submatrices from an H matrix;
a parity check calculator connected to the low density parity check decoder, operable to detect whether a stopping criterion has been met in the low density parity check decoder, the low density parity check decoder being operable to end a decoding operation at less than a maximum number of iterations when the stopping criterion is met, wherein the parity check calculator comprises:
a barrel shifter connected to an input of the parity check calculator, the barrel shifter being operable to shift the input from column order to row order;
a permutation circuit connected to the barrel shifter and operable to arrange non-zero elements in each circulant of the H matrix according to a parity check equation implemented by the parity check calculator;
a parity check calculation circuit connected to the barrel shifter and operable to implement the parity check equation;
a parity register connected to the parity check calculation circuit; and
a multi-stage adder connected to the parity register and operable to add a plurality of parity check results from the parity register to yield an unsatisfied check number and a convergence status.