IP Library › Granted Patent US 8,656,409
Granted Patent B2
US 8,656,409 · App. 12/087,182 · Granted Feb 18, 2014

High performance queue implementations in multiprocessor systems

Inventors: Xiao-Feng Li (Beijing, CN); Dz-ching Ju (Saratoga, CA)
Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,656,409
App. No.
12/087,182
Granted
Feb 18, 2014
Kind
B2
Abstract

Systems and methods provide a single reader single writer (SRSW) queue structure having entries that can be concurrently accessed in an atomic manner with a single memory access. The SRSW queues may be combined to create more complicated queues, including multiple reader single writer (MRSW), single reader multiple writer (SRMW), and multiple reader multiple writer (MRMW) queues.

Claims (45)

1. A system comprising:

a first queue having a plurality of first queue entries, each of the first queue entries occupying a memory portion atomically accessible in a single memory access;

a second queue having a plurality of second queue entries, each of the second queue entries occupying a memory portion atomically accessible in a single memory access;

a third queue having a plurality of third queue entries, each of the third queue entries occupying a memory portion atomically accessible in a single memory access;

a fourth queue having a plurality of fourth queue entries, each of the fourth queue entries occupying a memory portion atomically accessible in a single memory access;

a first thread to write to the first queue;

a second thread to write to the second queue;

a multiplexer thread to read the first queue and the second queue and to write to the third queue and the fourth queue;

a third thread to read from the third queue; and

a fourth thread to read from the fourth queue.

2. The system of claim 1 , wherein the first queue, the second queue, the third queue and the fourth queue are dynamically created.

3. The system of claim 1 , wherein the first queue, the second queue, the third queue and the fourth queue each have a plurality of queue entries, the queue entries having a valid value and a NULL value, and wherein during a read a queue entry of the plurality of queue entries is returned if the queue entry has the valid value and wherein during a write the queue entry is written if the queue entry has the NULL value.

4. The system of claim 1 , wherein the first queue includes a head value to identify a head entry of the plurality of first queue entries, and wherein the head value is aligned on a cache line boundary.

5. The system of claim 1 , wherein the first queue includes a tail value to identify a tail entry of the plurality of queue entries, and wherein the tail value is aligned on a cache line boundary.

6. The system of claim 1 , wherein the plurality of first queue entries are aligned on a cache line boundary and wherein the respective memory portions for each of the plurality of first queue entries are aligned a word boundary.

7. A method comprising:

initializing a first queue having a plurality of first queue entries, each of the first queue entries occupying a memory portion atomically accessible in a single memory access;

initializing a second queue having a plurality of second queue entries, each of the second queue entries occupying a memory portion atomically accessible in a single memory access;

initializing a third queue having a plurality of third queue entries, each of the third queue entries occupying a memory portion atomically accessible in a single memory access;

initializing a fourth queue having a plurality of fourth queue entries, each of the fourth queue entries occupying a memory portion atomically accessible in a single memory access;

using a first thread to write to the first queue;

using a second thread to write to the second queue;

using a multiplexer thread to read the first queue and the second queue and to write to the third queue and the fourth queue;

using a third thread to read from the third queue; and

using a fourth thread to read from the fourth queue.

8. The method of claim 7 , dynamically creating the first queue, the second queue, the third queue and the fourth queue.

9. The method of claim 7 , wherein the first queue, the second queue, the third queue and the fourth queue each have a plurality of queue entries, the queue entries having a valid value and a NULL value, and wherein during a read a queue entry of the plurality of queue entries is returned if the queue entry has the valid value and wherein during a write the queue entry is written if the queue entry has the NULL value.

10. The method of claim 7 , wherein the first queue includes a head value to identify a head entry of the plurality of first queue entries, and wherein the head value is aligned on a cache line boundary.

11. The method of claim 7 , wherein the first queue includes a tail value to identify a tail entry of the plurality of queue entries, and wherein the tail value is aligned on a cache line boundary.

12. The method of claim 7 , wherein the plurality of first queue entries are aligned on a cache line boundary and wherein the respective memory portions for each of the plurality of first queue entries are aligned a word boundary.

13. A non-transitory machine-readable medium including instructions that, when executed by the machine, cause the machine to perform operations comprising:

initializing a first queue having a plurality of first queue entries, each of the first queue entries occupying a memory portion atomically accessible in a single memory access;

initializing a second queue having a plurality of second queue entries, each of the second queue entries occupying a memory portion atomically accessible in a single memory access;

initializing a third queue having a plurality of third queue entries, each of the third queue entries occupying a memory portion atomically accessible in a single memory access;

initializing a fourth queue having a plurality of fourth queue entries, each of the fourth queue entries occupying a memory portion atomically accessible in a single memory access;

using a first thread to write to the first queue;

using a second thread to write to the second queue;

using a multiplexer thread to read the first queue and the second queue and to write to the third queue and the fourth queue;

using a third thread to read from the third queue; and

using a fourth thread to read from the fourth queue.

14. The machine-readable medium of claim 13 , wherein the operations include dynamically creating the first queue, the second queue, the third queue and the fourth queue.

15. The machine-readable medium of claim 13 , wherein the first queue, the second queue, the third queue and the fourth queue each have a plurality of queue entries, the queue entries having a valid value and a NULL value, and wherein during a read a queue entry of the plurality of queue entries is returned if the queue entry has the valid value and wherein during a write the queue entry is written if the queue entry has the NULL value.

16. The machine-readable medium of claim 13 , wherein the first queue includes a head value to identify a head entry of the plurality of first queue entries, and wherein the head value is aligned on a cache line boundary.

17. The machine-readable medium of claim 13 , wherein the first queue includes a tail value to identify a tail entry of the plurality of queue entries, and wherein the tail value is aligned on a cache line boundary.

18. The machine-readable medium of claim 13 , wherein the plurality of first queue entries are aligned on a cache line boundary and wherein the respective memory portions for each of the plurality of first queue entries are aligned a word boundary.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2013
From: LI, XIAO-FENG; JU, DZ-CHING
To: INTEL CORPORATION
Reel/Frame 029641/0851 →
Continuity (1)
Related Publication 20090133023A1 · May 21, 2009