Dynamic memory structure
A DRAM memory structure at least includes a strip semiconductive material disposed on a substrate and extending along a first direction, a split gate disposed on the substrate and extending along a second direction, a dielectric layer at least sandwiched between the split gate and the substrate, a gate dielectric layer at least sandwiched between the split gate and the strip semiconductive material, and a capacitor unit. The split gate independently includes a first block and a second block to divide the strip semiconductive material into a source terminal, a drain terminal and a channel. The capacitor unit is electrically connected to the source terminal.
1. A DRAM memory structure, comprising:
a substrate;
a first strip semiconductor material disposed on said substrate and extending along a first direction;
a split gate disposed on said substrate, extending along a second direction and comprising independently a first block and a second block to divide said first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region;
a first dielectric layer at least partially sandwiched between said split gate and said substrate;
a first gate dielectric layer at least partially sandwiched between said split gate and said strip semiconductor material; and
a first capacitor unit electrically connected to said first source terminal, wherein said first capacitor unit is disposed on said substrate and comprises said first source terminal serving as a bottom electrode, a second dielectric layer at least partially covering said first source terminal to serve as a capacitor dielectric layer, and a capacitor metal layer at least partially covering said second dielectric layer to serve as a top electrode.
2. The DRAM memory structure of claim 1 , wherein said substrate is a conductive Si substrate, an insulating Si substrate or the combination thereof.
3. The DRAM memory structure of claim 1 , wherein said first direction is substantially perpendicular to said second direction.
4. The DRAM memory structure of claim 1 , wherein said first direction crosses said second direction but said first direction is substantially not perpendicular to said second direction.
5. The DRAM memory structure of claim 1 , wherein said first dielectric layer and said second dielectric layer has one of a same high-k material and different high-k materials.
6. The DRAM memory structure of claim 1 , wherein said second dielectric layer covers up to five sides of said first source terminal.
7. The DRAM memory structure of claim 1 , wherein said capacitor metal layer completely covers said first source terminal.
8. The DRAM memory structure of claim 1 , wherein one of said first block and said second block is a drive gate and the other one is a back gate.
9. The DRAM memory structure of claim 8 , further comprising:
a word line electrically connected to said drive gate.
10. The DRAM memory structure of claim 8 , further comprising:
a back line electrically connected to said back gate.
11. The DRAM memory structure of claim 1 , wherein said first strip semiconductor material is higher than at least one of said first block and said second block.
12. The DRAM memory structure of claim 1 , wherein at least one of said first block and said second block is higher than said first strip semiconductor material.
13. The DRAM memory structure of claim 1 , wherein said split gate comprises a metal.
14. The DRAM memory structure of claim 1 , wherein said first strip semiconductor material, said first source terminal and said first drain terminal are integrally formed.
15. The DRAM memory structure of claim 1 , further comprising:
a bit line electrically connected to said first drain terminal.
16. The DRAM memory structure of claim 1 , further comprising:
a second strip semiconductor material disposed on said substrate and extending along said first direction, wherein said split gate further comprises a third block so that said second block and said third block together divide said second strip semiconductor material into a second source terminal, a second drain terminal and a second channel region;
a second gate dielectric layer at least partially sandwiched between said split gate and said second strip semiconductor material; and
a second capacitor unit electrically connected to said second source terminal.
17. The DRAM memory structure of claim 16 , wherein said second capacitor unit is disposed on said substrate and comprises said second source terminal serving as a bottom electrode, a second dielectric layer at least partially covering said second source terminal to serve as a second capacitor dielectric layer, and a capacitor metal layer at least partially covering said second dielectric layer to serve as a second top electrode, wherein said first source terminal is not in contact with said second source terminal.
18. The DRAM memory structure of claim 16 , wherein said first strip semiconductor material, said second strip semiconductor material, said split gate, said first capacitor unit and said second capacitor unit together form a dynamic memory unit.
19. The DRAM memory structure of claim 18 , wherein said first capacitor unit and said second capacitor unit together share a capacitor metal layer.
20. The DRAM memory structure of claim 18 , wherein said first capacitor unit and said second capacitor unit together share a back gate.