Semiconductor memory device and manufacturing method thereof
The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.
1. A semiconductor memory device comprising:
a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation layer and a plurality of electrodes formed around the second insulation film, the plurality of electrodes of a memory string being shared with the plurality of electrodes of other memory strings;
a plurality of bit lines respectively connected to one end of the plurality of memory strings via a plurality of selection transistors; and
a plurality of conductive layers including a memory transistor region and a contact region and extending in two dimensions, the memory transistor region being formed by the plurality of electrodes of the plurality of memory strings, the contact region being arranged in an end part of the plurality of conductive layers, the end part of the plurality of conductive layers being arranged in a first direction perpendicular to a bit line direction, the plurality of conductive layers in the contact region being formed in a step shape in the bit line direction, and both edges of the plurality of conductive layers in the memory transistor region in the bit line direction being aligned respectively.
2. The semiconductor memory device according to claim 1 , wherein both ends of the end part of the plurality of conductive layers are formed in a step shape in the bit line direction.
3. The semiconductor memory device according to claim 1 , wherein a plurality of word lead lines is each arranged on the end part of the plurality of conductive layers.
4. The semiconductor memory device according to claim 1 , wherein a plurality of contacts is each arranged on the end part of the plurality of conductive layers.
5. The semiconductor memory device according to claim 1 , wherein the plurality of conductive layers are each plate shaped.
6. The semiconductor memory device according to claim 1 , wherein the plurality of memory strings are arranged in a matrix in an in-plane surface perpendicular to the column shaped semiconductor.
7. The semiconductor memory device according to claim 1 , wherein the end part of the plurality of conductive layers is further formed in a step shape in the first direction.
8. A semiconductor memory device comprising:
a substrate;
a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the plurality of memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, the plurality of electrodes of a memory string being shared with the plurality of electrodes of other memory strings;
a plurality of bit lines respectively connected to one end of the plurality of memory strings via a plurality of selection transistors; and
a plurality of conductive layers including a memory transistor region and a contact region and extending in two dimensions, the memory transistor region being formed by the plurality of electrodes of the plurality of memory strings, the contact region being arranged in an end part of the plurality of conductive layers, the end part of the plurality of conductive layers being arranged in a first direction perpendicular to a bit line direction, the plurality of conductive layers in the contact region being formed in a step shape in the bit line direction, and both edges of the plurality of conductive layers in the memory transistor region in the bit line direction being aligned respectively,
wherein widths in the bit line direction of the plurality of conductive layers in the contact region each meet the following formula when one of the plurality of the conductive layers of the substrate side is a first conductive layer in the plurality of conductive layers:
a width of a (k -1)th conductive layer > a width of a kth conductive layer (k is an integer equal to or larger than 2).
9. The semiconductor memory device according to claim 8 , wherein both ends of the end part of the plurality of conductive layers are formed in a step shape in the bit line direction.
10. The semiconductor memory device according to claim 8 , wherein a plurality of word lead lines is each arranged on the end part of the plurality of conductive layers.
11. The semiconductor memory device according to claim 8 , wherein a plurality of contacts is each arranged on the end part of the plurality of conductive layers.
12. The semiconductor memory device according to claim 8 , wherein the plurality of memory strings are arranged in a matrix in an in-plane surface perpendicular to the column shaped semiconductor.
13. The semiconductor memory device according to claim 8 , wherein the end part of the plurality of conductive layers is further formed in a step shape in the first direction.