Method and system for performing self-tests in an electronic system

1. A method for performing a self-test of power supply quality for an integrated circuit chip within an electronic system, comprising:

subjecting said electronic system to a well-defined repetitive activity;

accumulating a set of time-domain measurement data of power supply voltage (U(t)) caused by said activity for a location on said chip;

transforming said time-domain measurement data of power supply voltage (U(t)) into a frequency-domain local voltage profile (U(f)); and

comparing said local voltage profile (U(f)) to a reference voltage profile (U 0 (f)).

2. The method according to claim 1 , further comprising:

evaluating a local impedance profile (Z(f)) from said local voltage profile (U(f)) and a current profile (I(f)) stored in a storage within system; and

comparing said local impedance profile (Z(f)) to a reference impedance profile (Z 0 (f)).

3. The method according to claim 2 , wherein said current profile (I(f)) is obtained from a temporal behavior of a current consumption (I(t)) due to said repetitive activity.

4. The method according to claim 3 , wherein said temporal behavior of a current consumption (I(t)) is determined analytically from quasistatic measurements of a leakage current (I leak ) obtained without said repetitive activity being applied and an active current (I 0 ) obtained with said repetitive activity being applied.

5. The method according to claim 1 , wherein said repetitive activity comprises periodically switching a system clock tree on and off.

6. The method according to claim 1 , wherein said repetitive activity is generated by a clock tree within a master/slave design, so that in case of failure of said electronic system, said repetitive activity is generated by a master clock while an actual system state is preserved by a slave clock set into an inactive state.

7. The method according to claim 1 , wherein said accumulating is performed by circuitry located wholly or partially on said chip.

8. The method according to claim 1 , wherein said method is carried out during a system power-on operation.

9. The method according to claim 1 , wherein said method is carried out periodically during system operation.

10. The method according to claim 1 , wherein said method is performed by a system integrated wholly or partially in said chip for which the self-test is to be executed.

11. A system for performing a self-test of power supply quality for an electronic system comprising an integrated circuit chip, comprising:

means for subjecting said electronic system to a well-defined repetitive activity;

means for accumulating a set of time-domain measurement data of power supply voltage (U(t)) caused by said activity for a location on said chip;

means for transforming said time-domain measurement data of power supply voltage (U(t)) into a frequency-domain local voltage profile (U(f)); and

means for comparing said local voltage profile (U(f)) to a reference voltage profile (U 0 (f)).

12. The system according to claim 11 , further comprising:

means for evaluating a local impedance profile (Z(f)) from said local voltage profile (U(f)) and a current profile (I(f)) stored in a storage within system; and

means for comparing said local impedance profile (Z(f)) to a reference impedance profile (Z 0 (f)).

13. The system according to claim 12 , wherein said current profile (I(f)) is obtained from a temporal behavior of a current consumption (I(t)) due to said repetitive activity.

14. The system according to claim 13 , wherein said temporal behavior of a current consumption (I(t)) is determined analytically from quasistatic measurements of a leakage current (I leak ) obtained without said repetitive activity being applied and an active current (I 0 ) obtained with said repetitive activity being applied.

15. The system according to claim 11 , wherein said repetitive activity comprises periodically switching a system clock tree on and off.

16. The system according to claim 11 , wherein said repetitive activity is generated by a clock tree within a master/slave design, so that in case of failure of said electronic system, said repetitive activity is generated by a master clock while an actual system state is preserved by a slave clock set into an inactive state.

17. The system according to claim 11 , wherein said means for accumulating comprises circuitry located wholly or partially on said chip.

18. The system according to claim 11 , wherein said system is integrated wholly or partially in said chip for which the self-test is to be executed.

19. The system according to claim 11 , wherein:

said means for applying a repetitive activity and said means for measuring a time-domain power supply voltage (U(t)) reside in said chip; and

said means for evaluating said local voltage profile (U(f)) and said means for comparing said local voltage profile to said reference voltage profile (U 0 (f)) reside in a location outside of said chip.

20. A system for performing a self-test of power supply quality for an electronic system comprising an integrated circuit chip, comprising:

a trigger unit and a clock modulation unit operable to subject said electronic system to a modulated clock signal representing a well-defined repetitive activity;

a measurement system, an analog-to-digital converter and a storage unit operable to accumulating a set of time-domain measurement data of power supply voltage (U(t)) caused by said activity for a location on said chip;

a transformation unit operable to transform said time-domain measurement data of power supply voltage (U(t)) into a frequency-domain local voltage profile (U(f)); and

a comparison unit operable to compare said local voltage profile (U(f)) to a reference voltage profile (U 0 (f)).