Semiconductor device and method of driving semiconductor device
View Patent ↗An object is to provide a semiconductor device to reduce variation in the threshold voltages of memory cells after writing, reduce the operation voltage, or increase the storage capacity. The semiconductor device includes memory cells each including a transistor including an oxide semiconductor, a driver circuit that drives the memory cells, a potential generating circuit that generates potentials supplied to the driver circuit, and a write completion detecting circuit that detects all at once whether rewriting of data into the memory cells is completed or not. The driver circuit includes a data buffer, a writing circuit that writes one potential of the potentials into each of the memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with the data held in the data buffer or not.
1. A semiconductor device comprising:
a memory cell;
a potential generating circuit;
a data buffer;
a writing circuit;
a reading circuit; and
a verifying circuit,
wherein the potential generating circuit is configured to generate a first potential and a second potential,
wherein the data buffer is configured to store first data,
wherein the writing circuit is configured to supply the first potential to the memory cell to write second data into the memory cell,
wherein the reading circuit is configured to read the second data from the memory cell,
wherein the verifying circuit is configured to verify whether the second data read by the reading circuit agrees with the first data stored by the data buffer or not, and
wherein the writing circuit is configured to supply the second potential to the memory cell to write third data into the memory cell in a case where the second data read by the reading circuit disagrees with the first data stored by the data buffer.
2. The semiconductor device according to claim 1 , wherein the first potential and the second potential are different from each other.
3. The semiconductor device according to claim 1 , wherein the memory cell comprises a transistor comprising an oxide semiconductor.
4. The semiconductor device according to claim 1 , wherein the memory cell comprises a first transistor comprising an oxide semiconductor and a second transistor comprising silicon.
5. The semiconductor device according to claim 1 ,
wherein the memory cell comprises a bit line,
wherein the writing circuit comprises a first transistor and a second transistor,
wherein the first transistor is configured to supply the first potential to the bit line to write the second data into the memory cell while a first voltage is supplied to a gate of the first transistor, and
wherein the second transistor is configured to supply the second potential to the bit line to write the third data into the memory cell while a second voltage is supplied to a gate of the second transistor.
6. The semiconductor device according to claim 1 ,
wherein the memory cell is electrically connected to a bit line,
wherein the writing circuit comprises a first transistor and a second transistor,
wherein the writing circuit comprises a third transistor, a fourth transistor, a first shift register, and a second shift register,
wherein the first transistor is configured to supply the first potential to the bit line to write the second data into the memory cell while a first terminal of the first shift register supplies a first voltage to a first terminal of the third transistor, a second terminal of the first shift register supplies a second voltage to a first terminal of the fourth transistor, and a first terminal of the second shift register supplies the first voltage to a gate of the third transistor and a gate of the fourth transistor, and
wherein the second transistor is configured to supply the second potential to the bit line to write the third data into the memory cell while the first terminal of the first shift register supplies the second voltage to the first terminal of the third transistor, the second terminal of the first shift register supplies the first voltage to the first terminal of the fourth transistor, and the first terminal of the second shift register supplies the first voltage to the gate of the third transistor and the gate of the fourth transistor.
7. The semiconductor device according to claim 1 ,
wherein the memory cell is electrically connected to a bit line and a word line,
wherein the reading circuit comprises a counter circuit and a latch circuit,
wherein the reading circuit is configured to decrease a potential of the word line,
wherein the counter circuit is configured to increase a counter value while the potential of the word line decreases, and
wherein the latch circuit is configured to latch the counter value when a voltage of the bit line is a first voltage.
8. A semiconductor device comprising:
a memory cell;
a potential generating circuit;
a writing circuit; and
a reading circuit,
wherein the potential generating circuit is configured to generate a first potential at a first terminal of the potential generating circuit and a second potential at a second terminal of the potential generating circuit
wherein the writing circuit is electrically connected to the first terminal of the potential generating circuit through a first signal line,
wherein the writing circuit is electrically connected to the second terminal of the potential generating circuit through a second signal line,
wherein the writing circuit is electrically connected to the memory cell through a third signal line, and
wherein the reading circuit is electrically connected to the memory cell through a fourth signal line.
9. The semiconductor device according to claim 8 , wherein the first potential and the second potential are different from each other.
10. The semiconductor device according to claim 8 ,
wherein the memory cell comprises a transistor comprising an oxide semiconductor, and
wherein a first terminal of the transistor is electrically connected to the third signal line.
11. The semiconductor device according to claim 8 ,
wherein the memory cell comprises a first transistor comprising an oxide semiconductor and a second transistor,
wherein a first terminal of the first transistor is electrically connected to the third signal line,
wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor, and
wherein a first terminal of the second transistor is electrically connected to the fourth signal line.
12. The semiconductor device according to claim 8 ,
wherein the writing circuit comprises a first transistor and a second transistor,
wherein a first terminal of the first transistor is electrically connected to the first signal line,
wherein a second terminal of the first transistor is electrically connected to the third signal line,
wherein a first terminal of the second transistor is electrically connected to the second signal line, and
wherein a second terminal of the second transistor is electrically connected to the third signal line.
13. The semiconductor device according to claim 8 ,
wherein the writing circuit comprises a first transistor and a second transistor,
wherein the writing circuit comprises a third transistor, a fourth transistor, a first shift register, and a second shift register,
wherein a first terminal of the first transistor is electrically connected to the first signal line,
wherein a second terminal of the first transistor is electrically connected to the third signal line,
wherein a gate of the first transistor is electrically connected to a first terminal of the third transistor,
wherein a first terminal of the second transistor is electrically connected to the second signal line,
wherein a second terminal of the second transistor is electrically connected to the third signal line,
wherein a gate of the second transistor is electrically connected to a first terminal of the fourth transistor,
wherein a second terminal of the third transistor is electrically connected to a first terminal of the first shift register,
wherein a gate of the third transistor is electrically connected to a first terminal of the second shift register,
wherein a second terminal of the fourth transistor is electrically connected to a second terminal of the first shift register, and
wherein a gate of the fourth transistor is electrically connected to the first terminal of the second shift register.
14. The semiconductor device according to claim 8 ,
wherein the reading circuit comprises a counter circuit, a latch circuit, and a transistor,
wherein the counter circuit is electrically connected to the latch circuit through the transistor, and
wherein a gate of the transistor is electrically connected to the fourth signal line.
15. A method for driving a semiconductor device, the semiconductor device comprising a memory cell and a data buffer, the method comprising the steps of:
storing first data in the data buffer;
supplying a first potential into the memory cell to store second data;
reading the second data from the memory cell; and
verifying whether the second data read from the memory cell agrees with the first data stored in the data buffer or not;
supplying a second potential into the memory cell to store third data in a case where the second data read from the memory cell disagrees with the first data stored in the data buffer.
16. The method for driving a semiconductor device according to claim 15 ,
wherein the second potential is smaller than the first potential in a case where the second data read from the memory cell is larger than the first data stored in the data buffer, and
wherein the second potential is larger than the first potential in a case where the second data read from the memory cell is smaller than the first data stored in the data buffer.
17. The method for driving a semiconductor device according to claim 15 , further comprising the steps of:
reading the third data from the memory cell;
verifying whether the third data read from the memory cell agrees with the first data stored in the data buffer or not; and
supplying a third potential into the memory cell to store fourth data in a case where the third data read from the memory cell disagree with the first data stored in the data buffer.
18. The method for driving a semiconductor device according to claim 17 ,
wherein the second potential is smaller than the first potential in a case where the second data read from the memory cell is larger than the first data stored in the data buffer,
wherein the second potential is larger than the first potential in a case where the second data read from the memory cell is smaller than the first data stored in the data buffer,
wherein the third potential is smaller than the first potential in a case where the third data read from the memory cell is larger than the first data stored in the data buffer, and
wherein the third potential is larger than the first potential in a case where the third data read from the memory cell is smaller than the first data stored in the data buffer.
19. The method for driving a semiconductor device according to claim 15 , the semiconductor device further comprising a writing circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a first shift register, and a second shift register, the method further comprising the steps of:
supplying the first potential into the memory cell through the first transistor while a first terminal of the first shift register supplies a first voltage to a first terminal of the third transistor, a second terminal of the first shift register supplies a second voltage to a first terminal of the fourth transistor, and a first terminal of the second shift register supplies the first voltage to a gate of the third transistor and a gate of the fourth transistor, and
supplying the second potential into the memory cell through the second transistor while the first terminal of the first shift register supplies the second voltage to the first terminal of the third transistor, the second terminal of the first shift register supplies the first voltage to the first terminal of the fourth transistor, and the first terminal of the second shift register supplies the first voltage to the gate of the third transistor and the gate of the fourth transistor.