IP Library › Granted Patent US 8,667,432
Granted Patent B2
US 8,667,432 · App. 13/887,672 · Granted Mar 4, 2014

Gate CD control using local design on both sides of neighboring dummy gate level features

Inventors: James Walter Blatchford (Richardson, TX); Yong Seok Choi (Kyunggi-do, KR); Thomas J. Aton (Dallas, TX)
Assignee: Texas Instrument Incorporated
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Quick Facts
Patent No.
US 8,667,432
App. No.
13/887,672
Granted
Mar 4, 2014
Kind
B2
Abstract

A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W 1 over an active area and a neighboring dummy feature having a line width 0.8 W 1 to 1.3 W 1 . The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Claims (8)

1. A non-transitory computer readable medium comprising program code that configures a processor to perform a method of designing a lithography mask set, the non-transitory computer readable medium comprising:

program code stored on physical computer media for forming a gate mask, said gate mask including neighboring dummy feature pitch restrictions, comprising:

a first active gate feature having a first line width W 1 over an active area and a neighboring dummy feature having a second line width=0.8 W 1 to 1.3 W 1 , said neighboring dummy feature having a first side adjacent to said first active gate feature, and a nearest gate level feature on a second side opposite to said first side;

wherein said neighboring dummy feature defines a gate pitch based on a distance to said first active gate feature or said neighboring dummy feature is positioned to maintain a gate pitch in a gate array including said first active gate feature; and

wherein a spacing between said neighboring dummy feature and said nearest gate level feature provides one of: (i) maintaining said gate pitch and (ii) being at a sub-resolution assist feature (SRAF) enabling distance that is ≧2 times said gate pitch and said gate mask includes a SRAF over said SRAF enabling distance.

2. The non-transitory computer readable medium of claim 1 , wherein said first active gate feature is one of a plurality of minimum size active end gates, and wherein at least a majority of said plurality of minimum size active end gates include said neighboring dummy feature pitch restrictions.

3. The non-transitory computer readable medium of claim 1 , wherein said SRAF is positioned for pitch-matching to both said neighboring dummy feature and said nearest gate feature when mask rules for said gate mask allow pitch-matching to both said neighboring dummy feature and said nearest gate level feature.

4. The non-transitory computer readable medium of claim 1 , wherein said SRAF is positioned in a center between said neighboring dummy feature and said nearest gate level feature when mask rules for said gate mask do not allow pitch-matching to both said neighboring dummy feature and said nearest gate level feature.

Continuity (2)
Division 12915974 · Oct 29, 2010
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