Multi-die stacking using bumps with different sizes
A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bonded to the first metal bump at the first side of the first die. A dielectric layer is formed over the first side of the first die and includes a first portion directly over the second die, a second portion covering the second die. A second metal bump of a second horizontal size greater than the first horizontal size is formed on the second region of the first side of the first die. An electrical component is bonded to the first side of the first die through the second metal bump.
1. A method of forming a device, the method comprising:
providing a wafer;
forming a first under-bump-metallurgy (UBM) and a second UBM over the wafer;
forming a first metal bump over and electrically coupled to the first UBM;
bonding a first die to the first metal bump;
forming a solder resist coating covering the first die and the wafer, the solder resist coating having a bottommost surface disposed above an uppermost surface of the second UBM;
forming an opening in the solder resist coating to expose at least a portion of the second UBM; and
forming a second metal bump in the opening and electrically coupled to the second UBM, wherein the second metal bump is larger than the first metal bump.
2. The method of claim 1 , wherein a portion of the second metal bump extends over the solder resist coating.
3. The method of claim 1 , further comprising forming a plurality of through vias inside the wafer.
4. The method of claim 1 , further comprising bonding an electrical component to the second metal bump, wherein electrical component is a device die or a package substrate.
5. The method of claim 4 , wherein after the step of bonding the electrical component, a ratio of a horizontal size of the second metal bump to a horizontal size of the first metal bump is greater than about 5.
6. The method of claim 1 , further comprising filling an underfill between the wafer and the first die before the step of forming the solder resist coating.
7. A method of forming a device, the method comprising:
providing a wafer;
forming a first under-bump-metallurgy (UBM) and a second UBM over the wafer;
forming a first metal bump over and electrically coupled to the first UBM;
bonding a first die to the first metal bump;
forming a dielectric layer covering the first die and the wafer;
forming an opening in the dielectric layer to expose at least a portion of the second UBM; and
forming a second metal bump in the opening and electrically coupled to the second UBM, wherein the second metal bump is larger than the first metal bump, and wherein the second bump extends below a bottommost surface of the dielectric layer.
8. The method of claim 7 , wherein a portion of the second metal bump extends over the dielectric layer.
9. The method of claim 7 , further comprising forming a plurality of through vias inside the wafer.
10. The method of claim 7 , further comprising bonding an electrical component to the second metal bump, wherein electrical component is a device die or a package substrate.
11. The method of claim 10 , wherein after the step of bonding the electrical component, a ratio of a horizontal size of the second metal bump to a horizontal size of the first metal bump is greater than about 5.
12. The method of claim 10 , further comprising filling an underfill between the electric component and an uppermost surface of the dielectric layer.
13. The method of claim 7 , further comprising filling an underfill between the wafer and the first die before the step of forming the dielectric layer.
14. A method of forming a device, the method comprising:
forming a first under-bump-metallurgy (UBM) and a second UBM over a first side of a substrate;
forming a first metal bump over and electrically coupled to the first UBM;
bonding a first die to the first metal bump;
forming a dielectric layer covering the first die, the second UBM and the substrate;
forming an opening in the dielectric layer to expose at least a portion of the second UBM; and
forming a second metal bump in the opening and electrically coupled to the second UBM, wherein the second metal bump is larger than the first metal bump, and wherein the second bump extends through the dielectric layer.
15. The method of claim 14 , wherein a portion of the second metal bump extends above a topmost surface of the dielectric layer.
16. The method of claim 14 , further comprising bonding an electrical component to the second metal bump, wherein electrical component is a device die or a package substrate.
17. The method of claim 16 , further comprising filling an underfill between the electric component and an uppermost surface of the dielectric layer.
18. The method of claim 16 , wherein after the step of bonding the electrical component, a ratio of a horizontal size of the second metal bump to a horizontal size of the first metal bump is greater than about 5.
19. The method of claim 14 , further comprising:
forming a through via through the substrate and extending from the first side of the substrate to a second side of the substrate opposite the first side, the through via in electrical contact to the first UBM.
20. The method of claim 19 , further comprising:
bonding a second electrical component to the second side of the substrate, the second electrical component electrically coupled to the die through the through via and the first UBM.