Multi-level chip input circuit
Aspects of the instant disclosure are directed toward apparatuses that generate a power-related adjustment signal in response to the power signal. Digital-input-signal pads are included to communicate digital signals with a circuit external to the apparatus. Further, digital-input processing circuitry receives the digital signals from the digital-input-signal pad, and processes the received digital signals. Additionally, configuration circuitry applies the power-related adjustment signal to signals received at the digital-input-signal pad and, in response, detects the digital signals received.
1. An apparatus comprising:
an integrated circuit (IC) having a power terminal connected to receive a power signal and having a decoding circuit, the decoding circuit including a signal-adjust circuit configured and arranged to generate a power-related adjustment signal in response to the power signal;
at least one digital-input-signal pad configured and arranged for communicating digital signals between the integrated circuit and another circuit which is external to the integrated circuit;
digital-input processing circuitry, within the IC and including binary logic circuitry, configured and arranged for receiving the digital signals from the digital-input-signal pad and for processing the received digital signals using the binary logic circuitry; and
configuration circuitry configured and arranged for applying the power-related adjustment signal to signals received at the at least one digital-input-signal pad and, in response thereto, for detecting that the digital signals received at the at least one digital-input-signal pad convey information using a first group of a plurality of states of information and at least two additional states of information, wherefrom more than the plurality of states of information in the first group are decoded from the information conveyed over the at least one digital-input-signal pad.
2. The apparatus of claim 1 , wherein the configuration circuitry includes analog circuitry configured and arranged to modulate the at least one digital-input signal pad by using the power-related adjustment signal to drive the at least one digital-input-signal pad.
3. The apparatus of claim 1 , further including the other circuit which is external to the integrated circuit.
4. The apparatus of claim 1 , wherein the configuration circuitry is further configured and arranged for applying the power-related adjustment signal to signals received at the at least one digital-input-signal pad in order to discern whether the digital signals received at the at least one digital-input-signal pad conveys information using a total number of states corresponding to the number of the first group of a plurality of states multiplied by the number of said at least two additional states of information.
5. The apparatus of claim 1 , wherein the more than the a plurality of states of information include: a floating input state; a high-level input state; a low-level input state; a low-ohmic input state; and a high-ohmic input state.
6. The apparatus of claim 1 , wherein the more than the plurality of states of information include: a floating input state; a high-level state; a low-level state; a low-ohmic high-level input state; a high-ohmic high-level input state; a low-ohmic low-level input state; and a high-ohmic low-level input state.
7. The apparatus of claim 1 , wherein the at least one digital-input-signal pad includes a first digital-input-signal pad and a second digital-input-signal pad, the first digital-input-signal pad configured and arranged to convey information using the first group of a plurality of states of information, and the second digital-input-signal pad configured and arranged to convey the at least two additional states of information.
8. The apparatus of claim 7 , wherein the first digital-input-signal pad is configured and arranged with the configuration circuitry and the digital-input processing circuitry for assessing the first group of a plurality of states of information and wherein the second digital-input-signal pad is configured and arranged with the configuration circuitry and the digital-input processing circuitry for assessing the at least two additional states of information.
9. The apparatus of claim 1 , wherein the configuration circuitry and the digital-input processing circuitry are configured and arranged to assess four states of information and to decode related information conveyed over the at least one digital-input-signal pad.
10. The apparatus of claim 1 , wherein the configuration circuitry and the digital-input processing circuitry are configured and arranged to assess five states of information and decode related information conveyed over the at least one digital-input-signal pad.
11. The apparatus of claim 1 , wherein the at least one digital-input-signal pad includes a first digital-input-signal pad and a second digital-input-signal pad configured and arranged with the configuration circuitry and the digital-input processing circuitry and wherein four states of information are decoded from the information conveyed over the first digital-input-signal pad and the second digital-input-signal pad.
12. The apparatus of claim 1 , wherein the at least one digital-input-signal pad includes a first digital-input-signal pad and a second digital-input-signal pad configured and arranged with the configuration circuitry and the digital-input processing circuitry and wherein five states of information are decoded from the information conveyed over the first digital-input-signal pad and the second digital-input-signal pad.
13. The apparatus of claim 1 , wherein the other circuit is external to the integrated circuit and connected to the at least one digital-input-signal pad and the binary logic circuitry includes a plurality of amplifiers configured and arranged to facilitate decoding of one or more of at least four states by a voltage level of the signals received at the at least one digital-input-signal pad.
14. The apparatus of claim 1 , wherein the more than the plurality of states of information include: a high-level input state; a low-level input state; a low-ohmic input state; and a high-ohmic input state.
15. An apparatus comprising:
an integrated circuit (IC) having a power terminal connected to receive a power signal and having a decoding circuit, the decoding circuit including a signal-adjust circuit configured and arranged to generate a power-related adjustment signal in response to the power signal;
at least one digital-input-signal pad configured and arranged for communicating digital signals between the integrated circuit and another circuit which is external to the integrated circuit;
digital-input processing circuitry, within the IC and including binary logic circuitry, configured and arranged for receiving the digital signals from the digital-input-signal pad and for processing the received digital signals using the binary logic circuitry; and
configuration circuitry configured and arranged for applying the power-related adjustment signal to signals received at the at least one digital-input-signal pad and, in response thereto, for detecting that the digital signals received at the at least one digital-input-signal pad convey information using a first group of a plurality of states of information and at least two additional states of information, wherefrom more than the four states of information, which includes a high-level input state; a low-level input state; a low-ohmic input state; and a high-ohmic input state, are decoded from the information conveyed over the at least one digital-input-signal pad and facilitate identification of the other circuit.
16. The apparatus of claim 15 , wherein the four states of information further includes a fifth state of information.
17. The apparatus of claim 16 , wherein the five states of information include: a floating input state; a high-level input state; a low-level input state; a low-ohmic input state; and a high-ohmic input state.
18. The apparatus of claim 15 , wherein the binary logic circuitry includes a plurality of amplifiers configured and arranged to facilitate decoding of one or more of at least four states by a voltage level of the signals received at the at least one digital-input-signal pad.
19. An apparatus comprising:
an integrated circuit (IC) having a power terminal connected to receive a power signal and having a decoding circuit, the decoding circuit including a signal-adjust circuit configured and arranged to generate a power-related adjustment signal in response to the power signal;
a first digital-input-signal pad and a second digital-input-signal pad configured and arranged for communicating digital signals between the integrated circuit and another circuit which is external to the integrated circuit;
digital-input processing circuitry, within the IC and including binary logic circuitry, configured and arranged for receiving the digital signals from the digital-input-signal pad and for processing the received digital signals using the binary logic circuitry; and
configuration circuitry configured and arranged for applying the power-related adjustment signal to signals received at the first digital-input-signal pad and the second digital-input-signal pad and, in response thereto, for detecting that the digital signals received at the at least one digital-input-signal pad convey information using a first group of a plurality of states of information and at least two additional states of information, wherefrom more than the four states of information are decoded from the information conveyed over the first digital-input-signal pad, and the second digital-input-signal pad multiplying the four states of information decoded from the information conveyed over the first digital-input-signal pad.
20. The apparatus of claim 19 , wherein the binary logic circuitry includes a plurality of amplifiers configured and arranged to facilitate decoding of one or more of at least four states by a voltage level of the signals received at the first digital-input-signal pad and the second digital-input-signal pad.