Phase control circuit

1. A phase control circuit comprising:

a first duty cycle correction circuit configured to correct a duty cycle of a clock signal;

a delay locked loop configured to perform delay locking of an output signal of the first duty cycle correction circuit;

a second duty cycle correction circuit configured to correct a duty cycle of an output signal of the delay locked loop;

an operating condition determination unit configured to determine a frequency information of the clock signal, and selectively activate one or more of the first duty cycle correction circuit, the second duty cycle correction circuit and the delay locked loop in response to the frequency information of the clock signal; and

an operating condition determination unit configured to determine the frequency information of the clock signal by comparing sampling values acquired by sampling the clock signal with a reference frequency information.

2. The phase control circuit according to claim 1 , wherein the first duty cycle correction circuit is configured to correct the duty cycle of the clock signal by controlling a slew rate of the clock signal.

3. The phase control circuit according to claim 1 , wherein the delay locked loop comprises a first loop and a second loop which are configured to independently adjust a delay time of the output signal of the first duty cycle correction circuit.

4. The phase control circuit according to claim 3 , wherein the second duty cycle correction circuit is configured to correct the duty cycle of the output signal of the delay locked loop by mixing phases of an output signal of the first loop and an output signal of the second loop.

5. The phase control circuit according to claim 1 , wherein the operating condition determination unit comprises:

a time/digital information converting section configured to compare the sampling values and the reference frequency information, and generate preliminary frequency information; and

a decoder configured to decode the preliminary frequency information and generate a signal for selectively activating the first duty cycle correction circuit and the second duty cycle correction circuit.

6. A phase control circuit comprising:

a first duty cycle correction circuit configured to correct a duty cycle of a clock signal and generate a reference clock signal;

a first loop configured to generate a first preliminary clock signal in response to the reference clock signal;

a second loop configured to generate a second preliminary clock signal in response to the reference clock signal;

a second duty cycle correction circuit configured to correct a duty cycle of the first preliminary clock signal using the second preliminary clock signal; and

an operating condition determination unit configured to determine a frequency information of the clock signal and selectively activate one or more of the first duty cycle correction circuit, the second duty cycle correction circuit and the second loop in response to the frequency information of the clock signal,

wherein, if the first duty cycle correction circuit is activated, the second duty cycle correction circuit and the second loop are deactivated.

7. The phase control circuit according to claim 6 , wherein, if the second duty cycle correction circuit and the second loop are activated, the first duty cycle correction circuit is deactivated.

8. The phase control circuit according to claim 6 , wherein the first duty cycle correction circuit is configured to correct the duty cycle of the clock signal by controlling a slew rate of the clock signal.

9. The phase control circuit according to claim 6 , wherein the first loop comprises:

a first delay line configured to delay the reference clock signal by a adjusted delay time and generate the first preliminary clock signal;

a first replica delay configured to delay the first preliminary clock signal by a preset delay time and output a first feedback clock signal; and

a first phase detector configured to compare phases of the first feedback clock signal and the reference clock signal and output a first phase comparison signal.

10. The phase control circuit according to claim 9 , wherein the second loop comprises:

a second delay line configured to delay the reference clock signal by a adjusted delay time and generate the second preliminary clock signal;

a second replica delay configured to delay the second preliminary clock signal by a preset delay time and output a second feedback clock signal; and

a second phase detector configured to compare phases of the second feedback clock signal and the reference clock signal and output a second phase comparison signal.

11. The phase control circuit according to claim 10 , further comprising:

a shift register configured to adjust delay times of the first delay line and the second delay line in response to the first phase comparison signal and the second phase comparison signal.

12. The phase control circuit according to claim 10 , wherein the second delay line and the second phase detector are configured to be activated when the second duty cycle correction circuit is activated.

13. The phase control circuit according to claim 6 , wherein the second duty cycle correction circuit is configured to mix phases of the first preliminary clock signal and the second preliminary clock signal.

14. The phase control circuit according to claim 6 , wherein the operating condition determination unit comprises:

a time/digital information converting section configured to compare sampling values acquired by sampling the clock signal and reference frequency information and generate preliminary frequency information; and

a decoder configured to decode the preliminary frequency information and generate a signal for selectively activating one or more of the first duty cycle correction circuit, the second duty cycle correction circuit and the second loop.

15. The phase control circuit according to claim 6 , wherein the operating condition determination unit is configured to determine the frequency information of the clock signal by comparing sampling values acquired by sampling the clock signal with a reference frequency information.