IP Library Granted Patent US 8,675,811
Granted Patent B2
US 8,675,811 · App. 12/734,595 · Granted Mar 18, 2014

Semiconductor device and display device

Inventors: Etsuo Yamamoto (Osaka, JP); Yasushi Sasaki (Osaka, JP); Yuhichiroh Murakami (Osaka, JP); Shige Furuta (Osaka, JP)
Assignee: Sharp Kabushiki Kaisha
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Quick Facts
Patent No.
US 8,675,811
App. No.
12/734,595
Granted
Mar 18, 2014
Kind
B2
Abstract

A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T 1 ) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T 2 ) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T 1 ). A gate terminal of the transistor (T 2 ) is connected to the source terminal of the transistor (T 2 ). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Claims (6)

1. A semiconductor device which is constituted by a plurality of transistors having an identical conductivity type, comprising:

a first transistor which has a first terminal to which an input signal is supplied and a second terminal from which an output signal is outputted;

a second transistor which has a first terminal to which a control signal is supplied and a second terminal which is connected to a control terminal of the first transistor;

a fourth transistor which has a first terminal connected to a point at which the control terminal of the first transistor and the second terminal of the second transistor are connected to each other, and a control terminal to which an ON voltage is supplied; and

a third transistor which has a first terminal connected to a second terminal of the fourth transistor, and a control terminal to which an inversion signal of the control signal is supplied,

a control terminal of the second transistor, the first terminal of the second transistor, and a second terminal of the third transistor being connected to one another.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2010
From: YAMAMOTO, ETSUO; SASAKI, YASUSHI; MURAKAMI, YUHICHIROH; FURUTA, SHIGE
To: SHARP KABUSHIKI KAISHA
Reel/Frame 024384/0958 →
Priority Claims (1)
JP 2007-339354 · Dec 28, 2007 · national
Continuity (1)
Related Publication 20100309184A1 · Dec 9, 2010