Switching a processor and memory to a power saving mode when waiting to access a second slower non-volatile memory on-demand

1. A computer system comprising:

a first nonvolatile memory that stores a first program, accepts read and write operations while operating at a first power consumption, and holds the first program while operating at a second power consumption smaller than the first power consumption;

a second nonvolatile memory that stores a second program or data, accepts read and write operations while operating at a third power consumption, and holds the stored program or data while operating at a fourth power consumption smaller than the third power consumption;

a processor that executes the first program or the second program at a fifth power consumption when receiving a restart instruction and stops execution of the first program or the second program at a sixth power consumption smaller than the fifth power consumption when receiving a temporary halt instruction;

a first power control circuit that causes the first nonvolatile memory to operate at the first power consumption and transmits the restart instruction to the processor when detecting change of an input signal to the processor, and causes the first nonvolatile memory to operate at the second power consumption and transmits the temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed; and

a second power control circuit that causes the second nonvolatile memory to operate at the third power consumption before the processor executes the second program, or before the processor reads the data, or before the processor writes the data,

wherein time necessary for the first nonvolatile memory to be able to accept the read and write operations from the processor from when the first power control circuit causes the first nonvolatile memory to operate at the first power consumption is shorter than time necessary for the second nonvolatile memory to be able to accept the read and write operations from the processor from when the second power control circuit causes the second nonvolatile memory to operate at the third power consumption.

2. The computer system according to claim 1 , wherein the second nonvolatile memory has a capacity larger than that of the first nonvolatile memory.

3. The computer system according to claim 2 , wherein the second power control circuit causes the second nonvolatile memory to operate at the fourth power consumption when the processor completes execution of the second program, or when the processor completes reading the data, or when the processor completes writing the data.

4. The computer system according to claim 3 , wherein

the processor performs setting so that an interrupt occurs after a predetermined time period when the second power control circuit causes the second nonvolatile memory to operate at the third power consumption, and

the first power control circuit causes the first nonvolatile memory to operate at the first power consumption and transmits the restart instruction to the processor on the basis of occurrence of the interrupt.

5. A method of controlling a computer system, the computer system including:

a first nonvolatile memory that stores a first program, accepts read and write operations while operating at a first power consumption, and holds the first program while operating at a second power consumption smaller than the first power consumption;

a second nonvolatile memory that stores a second program or data, accepts read and write operations while operating at a third power consumption, and holds the stored program or data while operating at a fourth power consumption smaller than the third power consumption; and

a processor that executes the first program or the second program at a fifth power consumption when receiving a restart instruction and stops execution of the first program or the second program at a sixth power consumption smaller than the fifth power consumption when receiving a temporary halt instruction, the method comprising:

causing the first nonvolatile memory to operate at the first power consumption and transmitting the restart instruction to the processor when a change of an input signal to the processor is detected;

causing the first nonvolatile memory to operate at the second power consumption and transmitting the temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed; and

causing the second nonvolatile memory to operate at the third power consumption before the processor executes the second program, or before the processor reads the data, or before the processor writes the data,

wherein time between the first nonvolatile memory is caused to operate at the first power consumption and the first nonvolatile memory accepts the read and write operations from the processor is shorter than time between the second nonvolatile memory is caused to operate at the third power consumption and the second nonvolatile memory accepts the read and write operations from the processor.

6. The method according to claim 5 , wherein the second nonvolatile memory has a capacity larger than that of the first nonvolatile memory.

7. The method according to claim 6 , further comprising

causing the second nonvolatile memory to operate at the fourth power consumption when the processor completes execution of the second program, or when the processor completes reading the data, or when the processor completes writing the data.

8. The method according to claim 7 , further comprising:

setting the processor to occur an interrupt after a predetermined time period when the second nonvolatile memory is caused to operate at the third power consumption; and

causing the first nonvolatile memory to operate at the first power consumption and transmitting the restart instruction to the processor on the basis of occurrence of the interrupt.