High throughput frame check sequence module architecture
Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products.
1. A method of processing a byte sequence into a cyclic redundancy check (CRC) value in a current pass, the method comprising:
dividing the byte sequence into blocks in one clock cycle, each block having a corresponding original width;
if a block's original width is less than a maximum number of bytes, padding the block until a new width is equal to the maximum number of bytes;
based on a first state vector and the padded block, computing, by a CRC unit, a first internal vector;
generating, by multiplying the internal vector by one or more first correction matrices, a first set of products; and
if the one or more first correction matrices form a complete set, selecting, in the one clock cycle, by a first control signal determined by the original width, a second state vector from the first set of products,
wherein the method is implemented as steps executed by a system-on-chip (SoC) network processor.
2. The method of claim 1 , wherein the first state vector, the first internal vector, the second state vector, and the CRC value are each comprised of 32 bits.
3. The method of claim 1 , the method further comprising:
storing the second state vector in a register.
4. The method of claim 3 , the method further comprising:
retrieving the second state vector from the register;
combining the second state vector with the first state vector; and
repeating the computing, generating, and selecting for a subsequent pass.
5. The method of claim 1 , wherein the maximum number of bytes is equal to 32 bytes.
6. The method of claim 1 , wherein, if the one or more first correction matrices are not the complete set, the complete set further comprising one or more second correction matrices, the method further comprising:
computing a ratio b and a remainder a by:
subtracting the original width from the maximum number of bytes, wherein the subtraction results in a difference; and
dividing the difference by an integer parameter n.
7. The method of claim 6 , the method further comprising:
selecting, by the first control signal further determined by the ratio b, a second internal vector from the first set of products;
generating, by multiplying the second internal vector by the one or more second correction matrices, a second set of products; and
selecting, by a second control signal determined by the remainder a, the second state vector from the second set of products.
8. A system-on-chip (SoC) network processor having a frame check sequence (FCS) module comprising:
a cyclic redundancy check (CRC) unit configured to receive a data block having a corresponding original width in one clock cycle, and compute a first internal vector based on a first state vector;
a set of first matrix units, each configured to multiply the first internal vector by a corresponding first correction matrix in parallel, wherein the multiplications result in a first set of products; and
a first multiplexer configured to select, in the one clock cycle, if the set of first matrix units forms a complete set and by a control signal determined by the original width, a second state vector from the first set of products.
9. The apparatus of claim 8 , wherein the first state vector, the first internal vector, the second state vector, and the CRC value are each comprised of 32 bits.
10. The apparatus of claim 8 , the invention further comprising a register configured to store the second state vector.
11. The apparatus of claim 10 , the CRC unit further configured to:
retrieve the second state vector from the register;
combine the second state vector with the first state vector for a subsequent pass.
12. The apparatus of claim 8 , wherein the maximum number of bytes is equal to 32 bytes.
13. The apparatus of claim 8 , wherein, if the set of first matrix units are not the complete set, the complete set further comprising a set of second matrix units, the apparatus further comprising:
an expansion unit configured to compute a remainder a and a ratio b based on the maximum number of bytes and the original width, wherein a second internal vector is further determined by the ratio b; and
a second multiplexer configured to select, by a second control signal determined by the remainder a, the second state vector from a second set of products, wherein
the set of second matrix units are each configured to multiply the second internal vector by a corresponding second correction matrix in parallel, wherein the multiplications result in the second set of products.
14. The apparatus of claim 13 , the invention further comprising:
a register configured to store the second state vector, wherein the second state vector is comprised of 32 bits.
15. A non-transitory, machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for processing a byte sequence into a cyclic redundancy check (CRC) value in a current pass, the method comprising:
dividing the byte sequence into blocks in one clock cycle, each block having a corresponding original width;
if a block's original width is less than a maximum number of bytes, padding the block until a new width is equal to the maximum number of bytes;
based on a first state vector and the padded block, computing, by a CRC unit, a first internal vector;
generating, by multiplying the first internal vector by one or more first correction matrices, a first set of products; and
if the one or more first correction matrices form a complete set, selecting, in the one clock cycle, by a first control signal determined by the original width, a second state vector from the first set of products,
wherein the non-transitory, machine-readable storage medium is implemented in a system-on-chip (SoC) network processor.
16. The non-transitory, machine-readable storage medium of claim 15 , further comprising:
storing the second state vector in a register;
retrieving the second state vector from the register;
combining the second state vector with the first state vector; and
repeating the computing, multiplying, and selecting for a subsequent pass.
17. The non-transitory, machine-readable storage medium of claim 15 , wherein the maximum number of bytes is equal to 32 bytes.
18. The non-transitory, machine-readable storage medium of claim 15 , wherein, if the one or more first correction matrices are not the complete set, the complete set further comprising one or more second correction matrices, the method further comprising:
computing a ratio b and a remainder a by:
subtracting the original width from the maximum number of bytes, wherein the subtraction results in a difference; and
dividing the difference by an integer parameter n.
19. The non-transitory, machine-readable storage medium of claim 18 , the method further comprising:
selecting, by the first control signal further determined by the ratio b, a second internal vector from the first set of products;
generating, by multiplying the second internal vector by the one or more second correction matrices, a second set of products; and
selecting, by a control signal determined by the remainder a, the second state vector from the second set of products.