Vertical channel memory devices with nonuniform gate electrodes and methods of fabricating the same
A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
1. A method comprising:
forming a mold stack comprising alternating insulation layers and sacrificial layers on a substrate;
forming vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack;
removing portions of the sacrificial layers in a first part of the mold stack to form first spaces and to leave portions of the sacrificial layers remaining between the insulation layers in a second part of the mold stack;
enlarging the first spaces by removing portions of the insulating layers and/or the vertical channel regions;
removing the remaining portions of the sacrificial layers in the second part of the mold stack to form second spaces between the insulating layers after enlarging the first spaces; and
forming gate electrodes in the first and second spaces.
2. The method of claim 1 , wherein the first part of the mold stack comprises an outer portion and wherein the second part of the mold stack comprises an inner portion.
3. The method of claim 1 , wherein forming gate electrodes is preceded by forming at least one data storage layer on sidewalls of the vertical channel regions and wherein forming gate electrodes comprises forming the gate electrodes on the at least one data storage layer.
4. The method of claim 1 , wherein enlarging the first spaces comprises increasing a width of the first spaces and/or increasing a height of the first spaces.
5. The method of claim 4 , wherein increasing a height of the first spaces comprises removing exposed portions of the insulation layers in the first spaces.
6. The method of claim 4 , wherein increasing a width of the first spaces comprises removing exposed portions of the vertical channel regions in the first spaces.
7. The method of claim 4 , wherein forming the first spaces and increasing the height of the first spaces are simultaneously performed, and wherein the increased height of the first spaces is gradually increased from a central portion of the mold stack toward edges of the mold stack.
8. The method of claim 1 , wherein removing portions of the sacrificial layers in a first part of the mold stack to form first spaces and to leave portions of the sacrificial layers remaining between the insulation layers in a second part of the mold stack comprises exposing sidewalls of the vertical channel regions adjacent the remaining sacrificial layers.
9. The method of claim 8 , wherein enlarging the first spaces includes removing exposed portions of the vertical channel regions in the first spaces to enlarge the first spaces.
10. The method of claim 1 , further comprising forming a cut defining a region that vertically penetrates at least an uppermost sacrificial layer among the sacrificial layers to divide the at least uppermost sacrificial layer into two separate portions.
11. The method of claim 1 , further comprising forming a cut defining a region that vertically penetrates at least an uppermost gate among the gates filling the second spaces to divide the at least uppermost gate into two separate portions.
12. The method of claim 1 , wherein the enlarged first spaces have a greater height than the second spaces.
13. A method comprising:
forming a mold stack comprising alternating insulation layers and sacrificial layers on a substrate;
forming vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack; and
forming gate electrodes between adjacent ones of the insulation layers and surrounding the vertical channel regions wherein the gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
14. The method of claim 13 , further comprising forming at least one data storage layer on the vertical channel regions before forming the gate electrodes and wherein forming gate electrodes comprises forming the gate electrodes on the at least one data storage layer.
15. The method of claim 13 , wherein the gate electrodes decrease in thickness away from the sidewalls of the insulation layers in a stepwise or gradual manner.