MOS device with memory function and manufacturing method thereof
View Patent ↗A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function. The method provides a processing which has high controllability and improves the performance of devices.
1. A manufacturing method of a MOS device with memory function, comprising:
providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer;
forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure;
forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure;
forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and
performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element wherein a portion of the compound layer containing oxygen element at the bottom of the opening has a memory function.
2. The manufacturing method of claim 1 , wherein the material of the alloy layer is Cu—Mg alloy, Cu—Mn alloy, Cu—Ni alloy, Cu—Co alloy, Cu—Zn alloy or Cu—Sn alloy.
3. The manufacturing method of claim 2 , wherein concentration of a metal, except Cu, in the alloy is from 1% to 99%.
4. The manufacturing method of claim 3 , wherein concentration of the metal in the alloy is from 1% to 20%.
5. The manufacturing method of claim 1 , wherein the alloy layer is formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition.
6. The manufacturing method of claim 1 , wherein after forming the opening and before forming the alloy layer, the manufacturing method further comprises: performing an oxidation treatment to the surface of the metal interconnect structure.
7. The manufacturing method of claim 6 , wherein the oxidation treatment to the surface of the metal interconnect structure is thermal oxidation or oxygen ion implantation.
8. The manufacturing method of claim 1 , wherein the metal interconnect structure is a W contact plug, a Cu contact plug, or a Cu trench or Cu via in metal interconnect.
9. The manufacturing method of claim 1 , wherein the alloy layer further overlies a surface of the second dielectric layer at a sidewall of the opening.
10. The manufacturing method of claim 1 , wherein a MOS transistor is formed in the semiconductor substrate, and the metal interconnect structure is electrically connected with a source and/or drain of the MOS transistor.
11. The manufacturing method of claim 1 , wherein after forming the alloy layer and before performing the thermal treatment, the manufacturing method further comprises: forming copper on the alloy layer to fill the opening.
12. The manufacturing method of claim 1 , wherein after performing the thermal treatment to the alloy layer and the metal interconnect structure, the manufacturing method further comprises: forming copper on the alloy layer to fill the opening.
13. A MOS device with memory function, comprising:
a semiconductor substrate;
a first dielectric layer overlying a surface of the semiconductor substrate, a metal interconnect structure being formed in the first dielectric layer;
a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure, an opening being formed in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; and
a barrier layer formed from an alloy layer;
wherein an alloy layer is formed at the bottom of the opening, and material of the alloy layer contains copper and other metal; and
wherein a portion of the alloy layer at the bottom of the opening has a memory function.
14. The MOS device with memory function of claim 13 , wherein the material of the barrier layer is MgO x , MnO x , NiO x , CoO x , ZnO x or SnO x .
15. The MOS device with memory function of claim 13 , wherein the metal interconnect structure is a W contact plug, a Cu contact plug, or a Cu trench or Cu via in metal interconnect.
16. The MOS device with memory function of claim 13 , wherein a MOS transistor is formed in the semiconductor substrate, and the metal interconnect structure is electrically connected with a source and/or drain of the MOS transistor.
17. The MOS device with memory function of claim 13 , further comprising copper on the barrier layer, the copper filling the opening.