Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate
There is provided a semiconductor wafer including a base wafer, an insulating layer, and a Si crystal layer in the stated order. The semiconductor wafer further includes an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer. The inhibition layer inhibiting crystal growth of a compound semiconductor. Furthermore, a seed crystal is provided within the opening, and a compound semiconductor has a lattice match or a pseudo lattice match with the seed crystal. There is also provided an electronic device includes a substrate, an insulating layer that is provided on the substrate, a Si crystal layer that is provided on the insulating layer, an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer, where the inhibition layer inhibits crystal growth of a compound semiconductor, a seed crystal that is provided within the opening, a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal, and a semiconductor device that is formed using the compound semiconductor.
1. A semiconductor wafer having a base wafer, an insulating layer, and a Si crystal layer in the stated order, the semiconductor wafer comprising
an inhibition layer disposed on the Si crystal layer, the inhibition layer having an opening penetrating therethrough to reach the Si crystal layer and inhibiting crystal growth of a compound semiconductor;
a seed crystal disposed within the opening;
a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal; and
a Si semiconductor device that is provided on a portion of the Si crystal layer, the portion being not covered by the seed crystal.
2. A semiconductor wafer having a base wafer, an insulating layer, and a Si crystal layer in the stated order, the semiconductor wafer comprising
an inhibition layer disposed on the Si crystal layer, the inhibition layer having an opening penetrating therethrough to reach the Si crystal layer and inhibiting crystal growth of a compound semiconductor;
a seed crystal disposed within the opening; and
a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal; and wherein
the base wafer is made of single crystal Si, and
the semiconductor wafer further comprises a Si semiconductor device that is provided on a portion of the base wafer, the portion being not covered by the seed crystal.
3. A semiconductor wafer s having a base wafer, an insulating layer, and a Si crystal layer in the stated order, the semiconductor wafer comprising
an inhibition layer disposed on the Si crystal layer, the inhibition layer having an opening penetrating therethrough to reach the Si crystal layer and inhibiting crystal growth of a compound semiconductor;
a seed crystal disposed within the opening;
a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal; wherein
the base wafer has a main plane that has an off angle with respect to the (100) plane or a plane crystallographically equivalent to the (100) plane,
the opening has a bottom shaped like a rectangle, and
one of the sides of the rectangle is substantially parallel to any one of the <010> direction, the <0-10> direction, the <001> direction, and the <00-1> direction of the base wafer.
4. The semiconductor wafer as set forth in claim 3 , wherein
the off angle is no less than 2° and no more than 6°.
5. A semiconductor wafer having a base wafer, an insulating layer, and a Si crystal layer in the stated order, the semiconductor wafer comprising
an inhibition layer disposed on the Si crystal layer, the inhibition layer having an opening penetrating therethrough to reach the Si crystal layer and inhibiting crystal growth of a compound semiconductor;
a seed crystal disposed within the opening; and
a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal; wherein
the base wafer has a main plane that has an off angle with respect to the (111) plane or a plane crystallographically equivalent to the (111) plane,
the opening has a bottom shaped like a hexagon, and
one of the sides of the hexagon is substantially parallel to any one of the <1-10> direction, the <−110> direction, the <0-11> direction, the <01-1> direction, the <10 −1 > direction, and the <−101> direction of the base wafer.
6. The semiconductor wafer as set forth in claim 5 , wherein
the off angle is no less than 2° and no more than 6°.