Method of operating memory controller, and memory system, memory card and portable electronic device including the memory controller
A method of operating a memory controller includes reading data from a first block of a memory device; detecting degraded pages from a plurality of pages of the first block and counting a number of the degraded pages in the first block; and recharging or reclaiming the first block, which includes the degraded pages, based on the counted number of the degraded pages.
1. A method of operating a memory controller, the method comprising:
reading data from a first block of a memory device;
detecting degraded pages from a plurality of pages of the first block and counting a number of the degraded pages in the first block, the degraded pages containing data having a programmed state distribution changed by charge loss;
performing a recharging operation when the counted number of the degraded pages is greater than a first reference value and less than or equal to a second reference value, the second reference value being greater than the first reference value; and
performing a reclaiming operation when the counted number of the degraded pages is greater than the second reference value, wherein
the recharging operation includes reprogramming error corrected bits of the data into a page of the first block having the same address as a page from which the data was read,
the reclaiming operation includes reprogramming error corrected bits of the data into a second block, the first block having a different physical address than the second block, and
the first block and the second block are in a same memory array of the memory device.
2. The method of claim 1 , wherein the page is determined to be a degraded page when a bit error rate of data read from a page of the first block is greater than a reference level.
3. The method of claim 1 , wherein a page is determined to be a degraded page when the page is unsuccessfully read using a first voltage, the page is read using a second read voltage and a difference between the first read voltage and the second read voltage is greater than a third reference value.
4. The method of claim 3 , wherein the page is read successfully read using the second read voltage.
5. The method of claim 1 , wherein a page is determined to be a degraded page based on time stamp information.
6. The method of claim 5 , wherein the time stamp information includes information about a time when a corresponding page was programmed, the time stamp information being stored in a spare region of the corresponding page.
7. A memory system comprising:
a nonvolatile memory device including a first block including a plurality of pages; and
a controller configured to control the nonvolatile memory device, the controller including,
a microprocessor configured to detect degraded pages from the plurality of pages of the first block, the degraded pages containing data having a programmed state distribution changed by charge loss; and
a counter configured to count a number of the detected degraded pages and send the counted number of the degraded pages to the microprocessor, the microprocessor being configured to,
perform a recharging operation when the counted number of the degraded pages is greater than a first reference value and less than or equal to a second reference value, the second reference value being greater than the first reference value, and
perform a reclaiming operation when the counted number of the degraded pages is greater than the second reference value, wherein
the microprocessor is configured to perform the recharging operation by reprogramming error corrected bits of data read from a the first block into a page of the first block having the same address as a page from which the data was read,
the microprocessor is configured to perform the reclaiming operation by reprogramming error corrected bits of the data into a second block,
the first block has a different physical address than the second block, and
the first and second blocks are in a same memory cell array of the nonvolatile memory device.
8. The memory system of claim 7 , wherein the microprocessor determines the page to be a degraded page when a bit error rate of data read from a page of the first block is greater than a reference level.
9. The memory system of claim 7 , wherein the microprocessor determines a page to be a degraded page if the page fails to be read using a first read voltage but is read successfully using a second read voltage, and a difference between the first read voltage and the second read voltage is greater than a third reference value.
10. A memory system comprising:
a memory device including a first block, the first block including a plurality of pages; and
a memory controller configured to control the memory device, the memory controller including,
a microprocessor configured to,
measure a voltage threshold shift of the plurality of pages, adjust a read voltage according to the voltage threshold shift, and detect degraded pages of the first block, the degraded pages containing data having a programmed state distribution changed by charge loss,
perform a recharging operation when the counted number of the degraded pages is greater than a first reference value and less than or equal to a second reference value, the second reference value being greater than the first reference value, and
perform a reclaiming operation when the counted number of the degraded pages is greater than the second reference value, and
a counter configured to count a number of the detected degraded pages of the first block and send the counted number to the microprocessor, wherein
the microprocessor is configured to perform the recharging operation by reprogramming error corrected bits of data read from a the first block into a page of the first block having the same address as a page from which the data was read,
the microprocessor is configured to perform the reclaiming operation by reprogramming error corrected bits of the data into a second block,
the first block has a different physical address than the second block, and
the first and second blocks are in a same memory cell array of the nonvolatile memory device.
11. The memory system of claim 10 , wherein the microprocessor is configured to determine a page to be a degraded page if a bit error rate of data read from a page of the first block is greater than a reference value.
12. The memory system of claim 10 , wherein the microprocessor is configured to determine a page to be a degraded page when the page is unsuccessfully read using a first voltage, the page is read using a second read voltage and a difference between the first read voltage and the second read voltage is greater than a third reference value.
13. The memory system of claim 12 , wherein the page is read successfully read using the second read voltage.
14. The memory system of claim 10 , wherein the microprocessor is configured to determine a page to be a degraded page based on time stamp information which includes information about a time when a corresponding page was programmed and is stored in a spare region of the corresponding page.