IP Library Granted Patent US 8,691,663
Granted Patent B2
US 8,691,663 · App. 12/613,863 · Granted Apr 8, 2014

Methods of manipulating stressed epistructures

Inventor: Mark W. Wanlass (Golden, CO)
Assignee: Alliance for Sustainable Energy, LLC
H01L31/1892H01L31/0352H01L21/02035
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Quick Facts
Patent No.
US 8,691,663
App. No.
12/613,863
Granted
Apr 8, 2014
Kind
B2
Abstract

A method of processing an epistructure or processing a semiconductor device including associating a conformal and flexible handle with the epistructure and removing the epistructure and handle as a unit from the parent substrate. The method further includes causing the epistructure and handle unit to conform to a shape that differs from the shape the epistructure otherwise inherently assumes upon removal from the parent substrate. A device prepared according to the disclosed methods.

Claims (29)

1. A method of processing an epistructure comprising:

growing an epistructure upon a parent substrate;

associating a conformal and flexible handle with the epistructure, wherein the handle comprises at least one of a flexible and conformal metal layer, a flexible and conformal plastic layer, a flexible and conformal dielectric layer, a flexible and conformal polymer layer, a flexible and conformal resin layer and a flexible and conformal semiconductor layer;

removing the epistructure and handle as a unit from the parent substrate; and

causing the epistructure and handle unit to conform to a shape that differs from the shape said epistructure otherwise inherently assumes upon removal from the parent substrate.

2. The method of processing an epistructure of claim 1 further comprising flattening the epistructure and handle unit.

3. The method of processing an epistructure of claim 2 further comprising flattening the epistructure and handle unit on a vacuum chuck.

4. The method of processing an epistructure of claim 2 further comprising associating the epistructure and handle unit with a flat secondary substrate or superstrate.

5. The method of processing an epistructure of claim 1 further comprising associating the handle with the epistructure with an intermediate bonding material.

6. The method of processing an epistructure of claim 1 wherein the epistructure comprises at least one layer of semiconductor material which is substantially lattice mismatched with the parent substrate.

7. The method of processing an epistructure of claim 1 wherein the epistructure comprises at least two layers of semiconductor material which are substantially lattice mismatched with each other.

8. The method of processing an epistructure of claim 1 wherein the epistructure comprises at least one layer of a selected Group III-V semiconductor alloy.

9. A method of fabricating a semiconductor device comprising:

growing an epistructure upon a parent substrate;

associating a conformal and flexible handle with the epistructure, wherein the handle comprises at least one of a flexible and conformal metal layer, a flexible and conformal plastic layer, a flexible and conformal dielectric layer, a flexible and conformal polymer layer, a flexible and conformal resin layer and a flexible and conformal semiconductor layer;

removing the epistructure and handle as a unit from the parent substrate; and

associating the epistructure and handle unit with a surface of one of a secondary substrate and a secondary superstrate wherein the surface has a selected shape which is different from a shape said epistructure otherwise inherently assumes upon removal from the parent substrate.

10. The method of fabricating a semiconductor device of claim 9 further comprising flattening the epistructure and handle unit.

11. The method of fabricating a semiconductor device of claim 9 further comprising associating the handle with the epistructure with an intermediate bonding material.

12. The method of fabricating a semiconductor device of claim 9 wherein the epistructure comprises at least one layer of semiconductor material which is substantially lattice mismatched with the parent substrate.

13. The method of fabricating a semiconductor device of claim 9 wherein the epistructure comprises at least two layers of semiconductor materials which are substantially lattice mismatched with each other.

14. The method of fabricating a semiconductor device of claim 9 further comprising removing the epistructure and handle from the parent substrate by at least one of chemical etching, lapping, a combination of lapping and etching, and ELO.

15. The method of fabricating a semiconductor device of claim 9 further comprising:

associating the epistructure and handle unit with an intermediate surface after removal from the parent substrate and before attaching the epistructure to a secondary substrate or superstrate, which intermediate surface has a shape which is different from the shape said epistructure otherwise inherently assumes upon removal from the parent substrate; and

performing a processing step upon the epistructure while the epistructure is associated with the intermediate surface.

16. The method of fabricating a semiconductor device of claim 15 wherein the intermediate surface is a vacuum chuck.

17. The method of fabricating a semiconductor device of claim 15 further comprising flattening the epistructure and handle unit on the intermediate surface.

18. The method of fabricating a semiconductor device of claim 9 wherein the epistructure comprises at least one layer of a selected Group III-V semiconductor alloy.

19. The method of fabricating a semiconductor device of claim 9 wherein the device is a photovoltaic cell.

Assignments (2)
EXECUTIVE ORDER 9424, CONFIRMATORY LICENSE Recorded Dec 16, 2009
From: ALLIANCE FOR SUSTAINABLE ENERGY, LLC
To: ENERGY, UNITED STATES DEPARTMENT OF
Reel/Frame 023665/0818 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2009
From: WANLASS, MARK
To: ALLIANCE FOR SUSTAINABLE ENERGY, LLC
Reel/Frame 023483/0033 →
Continuity (1)
Related Publication 20110108097A1 · May 12, 2011