IP Library Granted Patent US 8,697,483
Granted Patent B2
US 8,697,483 · App. 13/758,356 · Granted Apr 15, 2014

Method of forming contact and semiconductor device manufactured by using the method

Inventor: Ki Jun Yun (Gyeonggi-do, KR)
Assignee: Dongbu HiTek Co., Ltd.
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Quick Facts
Patent No.
US 8,697,483
App. No.
13/758,356
Granted
Apr 15, 2014
Kind
B2
Abstract

A method of forming a contact includes forming an inter-layer dielectric layer to cover a gate formed on a semiconductor substrate; and forming a first hole which passes through the inter-layer dielectric layer to expose the gate, a second hole which exposes an active region of the semiconductor substrate, and a third hole which exposes the semiconductor substrate at a preset depth. Further, the method includes forming a shielding layer on the semiconductor substrate including the bottom and sidewalls of the first hole, the second hole, and the third hole; and removing the shielding layer at the bottom of the first hole and the second hole to expose the gate and the active region. Furthermore, the method includes filling the first hole, the second hole, and the third hole with a conductive material.

Claims (11)

1. A method of forming a contact, the method comprising:

forming an inter-layer dielectric layer to cover a gate formed on a semiconductor substrate;

forming a first hole which passes through the inter-layer dielectric layer to expose the gate, a second hole which exposes an active region of the semiconductor substrate, and a third hole which exposes the semiconductor substrate at a preset depth;

forming a shielding layer on the semiconductor substrate including the bottoms and sidewalls of the first hole, the second hole, and the third hole;

removing the shielding layer at the bottoms of the first hole and the second hole to expose the gate and the active region; and

filling the first hole, the second hole, and the third hole with a conductive material.

2. The method of claim 1 , wherein said forming the first hole to the third hole is performed such that the third hole is formed through a separate step from the first hole and the second hole.

3. The method of claim 1 ,

wherein said exposing the gate and the active region includes

forming a mask pattern on the semiconductor substrate, on which the shielding layer is formed, to expose the first hole and the second hole; and

etching the shielding layer at the bottoms of the first and second holes at a preset length using the mask pattern.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2025
From: INTELLECTUAL DISCOVERY
To: CLAIRPATH, LLC
Reel/Frame 072430/0707 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2014
From: DONGBU HITEK CO., LTD
To: INTELLECTUAL DISCOVERY CO., LTD.
Reel/Frame 033831/0789 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2013
From: YUN, KI JUN
To: DONGBU HITEK CO., LTD.
Reel/Frame 029748/0699 →
Continuity (1)
Related Publication 20130277848A1 · Oct 24, 2013