Semiconductor device and method of manufacturing the same
A semiconductor device includes vertical channel layers, a pipe channel layer coupling bottoms of the vertical channel layers, a pipe gate contacting a bottom surface and side surfaces of the pipe channel layer, and a dummy pipe gate formed of a non-conductive material and contacting a top surface of the pipe channel layer.
1. A semiconductor device, comprising:
vertical channel layers;
a pipe channel layer coupling bottoms of the vertical channel layers;
a pipe gate contacting a bottom surface and side surfaces of the pipe channel layer;
a dummy pipe gate formed of a non-conductive material and contacting a top surface of the pipe channel layer;
word lines stacked over the dummy pipe gate, wherein a lowermost word line, among the word lines, contacts a top surface of the dummy pipe gate;
interlayer insulating layers interposed between the word lines; and
slits passing through the word lines and the interlayer insulating layers, wherein the slits are deep enough to expose the dummy pipe gate.
2. The semiconductor device of claim 1 , wherein the dummy pipe gate is formed of an undoped polysilicon layer.
3. The semiconductor device of claim 1 , wherein the pipe gate is formed of a doped polysilicon layer.
4. The semiconductor device of claim 1 , wherein the pipe gate comprises either a polysilicon layer including a first type of impurities or stacked polysilicon layers, each layer alternately comprising of the first type of impurities and a second type of impurities, wherein the first and second types of impurities are different from each other.
5. The semiconductor device of claim 1 , wherein the lowermost word line is configured as a dummy word line.
6. The semiconductor device of claim 1 , further comprising:
a memory layer surrounding the pipe channel layer and the vertical channel layers; and
an insulating layer surrounding the bottom and side surfaces of the pipe channel layer.
7. A semiconductor device, comprising:
vertical channel layers;
a pipe channel layer coupling bottoms of the vertical channel layers;
a pipe gate contacting a bottom surface and side surfaces of the pipe channel layer;
a dummy pipe gate formed of a non-conductive material and contacting a top surface of the pipe channel layer;
word lines stacked over the dummy pipe gate, wherein a lowermost word line, among the word lines, contacts a top surface of the dummy pipe gate;
interlayer insulating layers interposed between the word lines; and a charge blocking layer interposed between the dummy pipe gate and the lowermost word line.
8. The semiconductor device of claim 7 , wherein the dummy pipe gate is formed of an undoped polysilicon layer.
9. The semiconductor device of claim 7 , wherein the pipe gate is formed of a doped polysilicon layer.
10. The semiconductor device of claim 7 , wherein the pipe gate comprises either a polysilicon layer including a first type of impurities or stacked polysilicon layers, each layer alternately comprising of the first type of impurities and a second type of impurities, wherein the first and second types of impurities are different from each other.
11. The semiconductor device of claim 7 , wherein the lowermost word line is configured as a dummy word line.
12. The semiconductor device of claim 7 , further comprising:
a memory layer surrounding the pipe channel layer and the vertical channel layers; and
an insulating layer surrounding the bottom and side surfaces of the pipe channel layer.