Tunnel field effect transistor and method for manufacturing same
A tunnel field effect transistor is capable of operating at a low subthreshold and is able to be manufactured easily. The tunnel field effect transistor includes a group IV semiconductor substrate having a (111) surface and doped so as to have a first conductivity type, a group III-V compound semiconductor nanowire arranged on the (111) surface and containing a first region connected to the (111) surface and a second region doped so as to have a second conductivity type, a source electrode connected to the group IV semiconductor substrate; a drain electrode connected to the second region, and a gate electrode for applying an electric field to an interface between the (111) surface and the group III-V compound semiconductor nanowire, or an interface between the first region and the second region.
1. A tunnel field effect transistor comprising:
a group IV semiconductor substrate having a (111) surface and doped so as to have a first conductivity type;
a group III-V compound semiconductor nanowire arranged on the (111) surface of the group IV semiconductor substrate and containing a first region connected to the (111) surface of the group IV semiconductor substrate and a second region doped so as to have a second conductivity type different from the first conductivity type;
a source electrode that is not in contact with the group III-V compound semiconductor nanowire and is connected to the group IV semiconductor substrate;
a drain electrode connected to the second region of the group III-V compound semiconductor nanowire; and
a gate electrode for applying an electric field to an interface between the (111) surface of the group IV semiconductor substrate and the group III-V compound semiconductor nanowire.
2. The tunnel field effect transistor according to claim 1 , wherein the group IV semiconductor is silicon or germanium,
the group III-V compound semiconductor is InAs, InP, GaAs, GaN, InSb, GaSb, AlSb, AlGaAs, InGaAs, InGaN, AlGaN, GaNAs, InAsSb, GaAsSb, InGaSb, AlInSb, InGaAlN, AlInGaP, InGaAsP, GaInAsN, InGaAlSb, InGaAsSb or AlInGaPSb, and
a longitudinal axis of the group III-V compound semiconductor nanowire is perpendicular to a (111) surface of the group IV semiconductor substrate.
3. The tunnel field effect transistor according to claim 1 , further comprising a gate dielectric film arranged on a side surface of the group compound semiconductor nanowire, wherein:
the gate electrode is arranged on the gate dielectric film.
4. The tunnel field effect transistor according to claim 1 , wherein an interface between the (111) surface of the group IV semiconductor substrate and the group III-V compound semiconductor nanowire has neither dislocation nor defect.
5. A tunnel field effect transistor comprising:
a group IV semiconductor substrate containing a first region having a (111) surface and a second region doped so as to have a first conductivity type;
a group III-V compound semiconductor nanowire arranged on the (111) surface of the first region of the group IV semiconductor substrate and undoped or doped so as to have a second conductivity type different from the first conductivity type;
a source electrode connected to the group III-V compound semiconductor nanowire;
a drain electrode that is not in contact with the group III-V compound semiconductor nanowire and is connected to the second region of the group IV semiconductor substrate; and
a gate electrode for applying an electric field to an interface between the group III-V compound semiconductor nanowire and the (111) surface of the group IV semiconductor substrate.
6. The tunnel field effect transistor according to claim 5 , wherein the group IV semiconductor is silicon or germanium,
the group III-V compound semiconductor is InAs, InP, GaAs, GaN, InSb, GaSb, AlSb, AlGaAs, InGaAs, InGaN, AlCaN, GaNAs, InAsSb, GaAsSb, InGaSb, AlInSb, InGaAlN, AlInGaP, InGaAsP, GaInAsN, InGaAlSb, InGaAsSb or AlInGaPSb, and
a longitudinal axis of the group III-V compound semiconductor nanowire is perpendicular to the (111) surface of the first region of the group IV semiconductor substrate.
7. The tunnel field effect transistor according to claim 5 , further comprising a gate dielectric film that is arranged on the surface of the group IV semiconductor substrate, wherein:
the gate electrode is arranged on the gate dielectric film.
8. The tunnel field effect transistor according to claim 5 , wherein the interface between the (111) surface of the group IV semiconductor substrate and the group III-V compound semiconductor nanowire has neither dislocation nor defect.
9. A switch element comprising the tunnel field effect transistor according to claim 1 or 5 .