Bottom-notched SiGe FinFET formation using condensation

1. A method of forming an integrated circuit structure, the method comprising:

forming a silicon fin over a silicon substrate;

forming a silicon germanium layer on a top surface and sidewalls of the silicon fin;

forming an undercut in an insulation region directly underlying and contacting the SiGe layer to expose a sidewall of a silicon extension region directly underlying the silicon fin; and

performing a condensation to convert the silicon germanium layer and the silicon fin into a silicon germanium (SiGe) fin and a silicon oxide layer on a top surface and opposite sidewalls of the SiGe fin.

2. The method of claim 1 , wherein the SiGe fin comprises a top portion having a first width, and a neck region underlying the top portion and having a second width smaller than the first width.

3. The method of claim 2 , wherein after the step of performing the condensation, the silicon oxide layer extends to directly underlying the neck region and electrically insulates the SiGe fin from the silicon substrate.

4. The method of claim 1 further comprising:

removing the silicon oxide layer from the top surface and from at least upper portions of the opposite sidewalls of the SiGe fin;

forming a gate dielectric of a FinFET on the top surface and the opposite sidewalls of the SiGe fin; and

forming a gate electrode of the FinFET on the gate dielectric.

5. The method of claim 4 , wherein after the step of removing the silicon oxide layer, an entirety of the silicon oxide layer is removed.

6. The method of claim 4 , wherein after the step of removing the silicon oxide layer, an upper portion of the silicon oxide layer is removed, and a lower portion of the silicon oxide layer is not removed.

7. The method of claim 6 further comprising:

after the step of performing the condensation, filling a sacrificial dielectric material contacting the silicon oxide layer;

recessing the sacrificial dielectric material until a top surface of the sacrificial dielectric material is level with an interface between the upper portion and the lower portion of the silicon oxide layer, wherein the silicon oxide layer is not recessed; and

removing the upper portion of the silicon oxide layer not protected by the sacrificial dielectric material; and

after the step of removing the upper portion of the silicon oxide layer, removing the sacrificial dielectric material.

8. The method of claim 6 further comprising:

after the step of performing the condensation, filling a dielectric material contacting the silicon oxide layer until a top surface of the dielectric material is higher than a top surface of the silicon oxide layer; and

recessing the dielectric material and the silicon oxide layer simultaneously until the upper portion of the silicon oxide layer is fully removed, wherein after the step of forming the gate electrode, the gate electrode comprises a portion directly over a remaining portion of the dielectric material.

9. A method of forming an integrated circuit structure, the method comprising:

forming two insulation regions in a silicon substrate, with an extension portion of the silicon substrate between and adjoining the two insulation regions;

recessing the two insulation regions, wherein a top part of the extension portion of the silicon substrate forms a silicon fin above remaining portions of the two insulation regions;

epitaxially growing a silicon germanium (SiGe) layer on a top surface and sidewalls of the silicon fin;

recessing the remaining portions of the two insulation regions to form an undercut under the SiGe layer; and

performing a condensation to convert the SiGe layer into silicon oxide and the silicon fin into a SiGe fin, resulting in a silicon oxide layer on a top surface and sidewalls of the SiGe fin.

10. The method of claim 9 , wherein the SiGe fin comprises a top portion having a first width, and a neck region underlying the top portion and having a second width smaller than the first width.

11. The method of claim 10 , wherein the silicon oxide layer extends directly underlying the neck region to electrically insulate the SiGe fin from the silicon substrate.

12. The method of claim 9 further comprising performing a gap-filling to fill a dielectric material to contact the silicon oxide layer, wherein the dielectric material is filled until a top surface of the dielectric material is higher than a top surface of the silicon oxide layer.

13. The method of claim 12 further comprising:

recessing the dielectric material until a top surface of the dielectric material is lower than a top surface of the SiGe fin;

removing exposed portions of the silicon oxide layer not protected by remaining portions of the dielectric material;

forming a gate dielectric of a FinFET on the top surface and the sidewalls of the SiGe fin, wherein the gate dielectric extends to directly over the remaining portions of the dielectric material; and

forming a gate electrode of the FinFET on the gate dielectric.

14. The method of claim 12 further comprising:

recessing the dielectric material until a top surface of the dielectric material is lower than a top surface of the SiGe fin;

removing exposed portions of the silicon oxide layer not protected by the dielectric material;

removing all remaining portions of the dielectric material;

forming a gate dielectric on the top surface and the sidewalls of the SiGe fin; and

forming a gate electrode on the gate dielectric.

15. The method of claim 9 further comprising:

removing an entirety of the silicon oxide layer; and

forming a gate dielectric on the top surface and the sidewalls of the SiGe fin; and

forming a gate electrode on the gate dielectric.

16. A method of forming an integrated circuit structure, the method comprising:

forming a silicon fin over a silicon substrate, the silicon fin extending from the silicon substrate;

forming two insulation regions on opposite sides of the silicon fin, an extension portion of the silicon substrate between and adjoining the two insulation regions;

epitaxially growing a silicon germanium (SiGe) layer on a top surface and sidewalls of the silicon fin;

recessing the two insulation regions to form an undercut under the SiGe layer; and

performing a condensation to convert the SiGe layer into silicon oxide and the silicon fin into a SiGe fin, resulting in a silicon oxide layer on a top surface and sidewalls of the SiGe fin, the SiGe fin comprising a top portion having a first width, and a neck region underlying the top portion and having a second width smaller than the first width.

17. The method of claim 16 , wherein the SiGe fin is electrically coupled to the silicon substrate through the neck region.

18. The method of claim 16 further comprising:

removing the silicon oxide layer from the top surface and from at least upper portions of the opposite sidewalls of the SiGe fin;

forming a gate dielectric of a FinFET on the top surface and the opposite sidewalls of the SiGe fin, the gate dielectric having a bottom end contacting a top end of the silicon oxide layer; and

forming a gate electrode of the FinFET on the gate dielectric.

19. The method of claim 16 further comprising:

after the step of performing the condensation, filling a sacrificial dielectric material contacting the silicon oxide layer;

recessing the sacrificial dielectric material until an upper portion of the silicon oxide layer is exposed; and

removing the upper portion of the silicon oxide layer not protected by the sacrificial dielectric material; and

after the step of removing the upper portion of the silicon oxide layer, removing the sacrificial dielectric material.