Input buffer protection

1. An apparatus comprising:

an input terminal of a first transistor to receive an input signal;

a control terminal of the first transistor to couple to a source of an electrical potential;

a channel to be induced in the first transistor by the electrical potential of the control terminal, wherein conductivity of the channel between the input terminal and an output terminal of the first transistor is increased when the electrical potential of the control terminal is increased by the input signal; and

a second transistor coupled in parallel with the first transistor in a component, the second transistor including a control terminal coupled to an internal supply voltage that is lower than an external supply voltage during a power down mode of operation of the component when the input signal is received.

2. The apparatus of claim 1 , wherein the first transistor and the second transistor are in a buffer circuit in the component.

3. The apparatus of claim 1 , wherein:

the output terminal of the first transistor is configured to receive the input signal from the input terminal through the channel; and

the input terminal, the control terminal, and the output terminal of the first transistor are configured to protect circuits coupled to the output terminal from electrostatic discharge from a port coupled to the input terminal.

4. The apparatus of claim 1 , wherein the source of the electrical potential is a circuit configured to enable the increase of the electrical potential of the control terminal of the first transistor induced by an increase in the input signal.

5. A method comprising:

receiving an input signal at an input terminal of a first transistor and a second transistor coupled in parallel with the first transistor in a component, the input signal to boost an electrical potential of a control terminal of the first transistor to increase conductivity of a channel between the input terminal and an output terminal of the first transistor; and

lowering an electrical potential of a control terminal of the second transistor during a power down mode of operation of the component.

6. The method of claim 5 , wherein receiving the input signal at the input terminal of the first transistor further comprises receiving a clock enable signal at the input terminal of the first transistor, the first transistor being configured to protect circuits coupled to the output terminal from electrostatic discharge.

7. The method of claim 5 , wherein lowering an electrical potential of a control terminal of the second transistor further comprises lowering an internal supply voltage below an external supply voltage during the power down mode of operation of the component when the input signal is received at the input terminal of the first transistor, the internal supply voltage to be coupled to the control terminal of the second transistor, the second transistor being coupled between the input signal and the output terminal.

8. A method comprising:

receiving an input signal at an input terminal of a first transistor and an input terminal of a second transistor in a component;

reducing an electrical potential of a control terminal of the first transistor; and

enabling an increase of an electrical potential of a control terminal of the second transistor in response to an increase in the input signal to render the second transistor more conductive to the input signal.

9. The method of claim 8 , wherein reducing the electrical potential of the control terminal of the first transistor further comprises:

coupling an internal supply voltage to the control terminal of the first transistor;

generating the internal supply voltage to render the first transistor conductive, the internal supply voltage being greater than an external supply voltage; and

reducing the internal supply voltage below the external supply voltage during a power down mode of operation of the component.

10. The method of claim 8 , further comprising:

charging the control terminal of the second transistor to an initial electrical potential before enabling the increase of the electrical potential of the control terminal of the second transistor.

11. The method of claim 8 , wherein enabling an increase of the electrical potential of the control terminal of the second transistor further comprises:

enabling an increase of the electrical potential of the control terminal of the second transistor during a power down mode of operation of the component.

12. The method of claim 8 , wherein receiving the input signal further comprises:

receiving a command signal having a transition to indicate an end to a power down mode of operation of the component.

13. The method of claim 8 , wherein receiving the input signal at the input terminal of the first transistor and the input terminal of the second transistor comprises:

protecting circuits coupled to the first transistor and the second transistor from electrostatic discharge at a port configured to receive the input signal.

14. A system comprising:

a first component coupled to a bus to receive an input signal from a second component through a buffer circuit, the buffer circuit comprising:

a first transistor including an input terminal coupled to receive the input signal and a control terminal coupled to receive an internal supply voltage, the internal supply voltage being higher than an external supply voltage during a normal mode of operation of the first component and lower than the external supply voltage during a power down mode of operation of the first component; and

a second transistor coupled in parallel with the first transistor, the second transistor including an input terminal coupled to the input terminal of the first transistor to receive the input signal, the second transistor including a control terminal at a voltage to be increased by the input signal on the input terminal to increase conductivity of the second transistor.

15. The system of claim 14 , wherein:

the second component comprises a processor coupled to the bus to generate external command signals on the bus; and

the first component comprises a dynamic random access memory device coupled to the bus to receive the external command signals, the input signal being one of the external command signals.

16. The system of claim 14 , wherein the input signal comprises:

a clock enable signal to indicate a validity of a clock signal received by the first component.

17. The system of claim 14 , wherein:

the first transistor includes an output terminal coupled to circuits; and

the second transistor includes an output terminal coupled to the circuits, the input signal being coupled from the input terminals to the output terminals of the first transistor and the second transistor when at least one of the first transistor or the second transistor is switched on.

18. The system of claim 14 , wherein:

the buffer circuit includes an electrostatic discharge protection circuit coupled to the input terminals of the first transistor and the second transistor; and

the first transistor and the second transistor are included in a voltage limiter circuit, the electrostatic discharge protection circuit and the voltage limiter circuit being configured to protect circuits in the first component from electrostatic discharge.

19. The system of claim 14 , wherein:

the first transistor comprises an n-type channel metal oxide semiconductor (MOS) pass gate transistor; and

the second transistor comprises an n-type channel MOS pass gate transistor.

20. A method comprising:

receiving an input signal at an input terminal of a first transistor and an input terminal of a second transistor in a component;

receiving an internal supply voltage at a control terminal of the first transistor, the internal supply voltage being higher than an external supply voltage during a normal mode of operation of the component and lower than the external supply voltage during a power down mode of operation of the component; and

enabling an increase of an electrical potential of a control terminal of the second transistor in response to an increase in the input signal to render the second transistor more conductive.

21. The method of claim 20 , wherein receiving an input signal further comprises:

receiving a clock enable signal to indicate a validity of a clock signal.

22. The method of claim 20 , further comprising:

charging the control terminal of the second transistor to an initial electrical potential before enabling the increase of the electrical potential of the control terminal of the second transistor.

23. The method of claim 20 , wherein receiving the input signal further comprises:

receiving a command signal having a transition to indicate an end to the power down mode of operation in the component.

24. The method of claim 20 , wherein receiving the input signal at the input terminal of the first transistor and the input terminal of the second transistor comprises:

protecting circuits coupled to the first transistor and the second transistor from electrostatic discharge at a port configured to receive the input signal.

25. A memory device comprising:

a memory array;

a control logic circuit coupled to the memory array to manage read and write operations in the memory array; and

an input buffer circuit coupled to the control logic circuit to receive a command signal, the input buffer circuit comprising:

a first transistor including an input terminal coupled to receive the command signal and a control terminal coupled to receive an internal supply voltage, the internal supply voltage being higher than an external supply voltage during a normal mode of operation of the memory device and lower than the external supply voltage during a power down mode of operation of the memory device; and

a second transistor coupled in parallel with the first transistor, the second transistor including an input terminal coupled to the input terminal of the first transistor to receive the command signal, the second transistor including a control terminal at a voltage that is to be increased by the command signal on the input terminal to render the second transistor more conductive.

26. The memory device of claim 25 , wherein the memory device comprises a dynamic random access memory device.

27. The memory device of claim 25 , wherein:

the input buffer circuit includes an electrostatic discharge protection circuit coupled to the input terminals of the first transistor and the second transistor; and

the first transistor and the second transistor are included in a voltage limiter circuit, the electrostatic discharge protection circuit and the voltage limiter circuit being configured to protect circuits in the memory device from electrostatic discharge.

28. The memory device of claim 25 , wherein the input buffer circuit is coupled to a bus to receive the command signal from a component coupled to the bus.

29. The memory device of claim 28 , wherein the component comprises a processor coupled to the bus to generate external command signals on the bus including the command signal.

30. The memory device of claim 29 , wherein the command signals comprise at least one of:

a chip select signal;

a clock signal;

a clock enable signal to indicate a validity of the clock signal;

a row address strobe signal to capture an address input and open a row in the array corresponding to the address input;

a column address strobe signal to capture an address input and select a column in the memory array corresponding to the address input;

a write enable signal to determine whether the column address strobe signal initiates a read operation or a write operation; or

a data-mask signal to control data input and data output between the memory device and a data bus.