Semiconductor memory device and method of operating the same
A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.
1. A method of operating a semiconductor memory device, comprising:
performing a first program operation in order to raise threshold voltages of memory cells coupled to a selected word line;
performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower by the first program operation, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage; and
performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.
2. The method of claim 1 , wherein the program verification operation comprises:
a first sub-verification operation for comparing each of the threshold voltages of the memory cells with the first sub-verification voltage by supplying the first sub-verification voltage to the memory cells,
a second sub-verification operation for comparing each of the threshold voltages of the memory cells with the second sub-verification voltage by supplying the second sub-verification voltage to the memory cells, and
a target verification operation for comparing each of the threshold voltages of the memory cells with the target verification voltage by supplying the target verification voltage to the memory cells.
3. The method of claim 1 , further comprising raising a level of a program voltage supplied to the memory cells, before performing the second program operation,
wherein the program verification operation, the rise in the level of the program voltage, and the second program operation are repeatedly performed until each of the threshold voltages of the memory cells becomes higher than the target verification voltage.
4. The method of claim 1 , wherein when the second program operation is performed,
a first program permission voltage is supplied to bit lines of memory cells, each having a threshold voltage lower than the second sub-verification voltage,
a second program permission voltage higher than the first program permission voltage is supplied to bit lines of the fast program memory cells, and
a program inhibition voltage higher than the second program permission voltage is supplied to bit lines of memory cells, each having a threshold voltage higher than the target verification voltage.
5. A method of operating a semiconductor memory device, comprising:
performing a first program operation in order to raise threshold voltages of memory cells coupled to a selected word line;
performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower by the first program operation, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage; and
performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the first sub-verification voltage, is greater than an increment of each of the threshold voltages of the fast program memory cells and an increment of each of threshold voltages of memory cells, which is higher than the first sub-verification voltage and lower than the target verification voltage.
6. The method of claim 5 , wherein the program verification operation comprises:
a first sub-verification operation for comparing each of the threshold voltages of the memory cells with the first sub-verification voltage by supplying the first sub-verification voltage to the memory cells,
a second sub-verification operation for comparing each of the threshold voltages of the memory cells with the second sub-verification voltage by supplying the second sub-verification voltage to the memory cells, and
a target verification operation for comparing each of the threshold voltages of the memory cells with the target verification voltage by supplying the target verification voltage to the memory cells.
7. The method of claim 5 , further comprising raising a level of a program voltage supplied to the memory cells, before performing the second program operation,
wherein the program verification operation, the rise in the level of the program voltage, and the second program operation are repeatedly performed until each of the threshold voltages of the memory cells becomes higher than the target verification voltage.
8. The method of claim 5 , wherein the second program operation is performed under a condition that an increment of each of threshold voltages of memory cells which is higher than the first sub-verification voltage, but lower than the target verification voltage, is greater than an increment of each of the threshold voltages of the fast program memory cells.
9. The method of claim 8 , wherein when the second program operation is performed,
a first program permission voltage is supplied to bit lines of memory cells, each having the threshold voltage lower than the second sub-verification voltage,
a second program permission voltage higher than the first program permission voltage is supplied to bit lines of memory cells, each having a threshold voltage higher than the first subverification voltage and lower than the target verification voltage,
a third program permission voltage higher than the second program permission voltage is supplied to bit lines of the fast program memory cells, and
a program inhibition voltage higher than the third program permission voltage is supplied to bit lines of memory cells, each having a threshold voltage higher than the target verification voltage.
10. A semiconductor memory device, comprising:
a memory array configured to comprise memory cells;
an operation circuit group configured to perform a program operation for the memory cells coupled to a selected word line and to detect fast program memory cells coupled to the selected word line, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower by the program operation, by using a target verification voltage and the first sub-verification voltage and the second subverification voltage which are sequentially lower than the target verification voltage; and
a control circuit configured to control the operation circuit group in order to perform the program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.
11. The semiconductor memory device of claim 10 , wherein when the second program operation is performed, the operation circuit group is configured to:
supply a first program permission voltage to bit lines of memory cells, each having a threshold voltage lower than the second sub-verification voltage,
supply a second program permission voltage higher than the first program permission voltage to bit lines of the fast program memory cells, and
supply a program inhibition voltage higher than the second program permission voltage to bit lines of memory cells, each having a threshold voltage higher than the target verification voltage.
12. The semiconductor memory device of claim 10 , wherein the control circuit controls the operation circuit group so that the second program operation is performed under a condition that an increment of each of threshold voltages of memory cells, which is lower than the first sub-verification voltage, is greater than an increment of each of threshold voltages of memory cells, which is higher than the first sub-verification voltage and lower than the target verification voltage.
13. The semiconductor memory device of claim 12 , wherein when the second program operation is performed, the operation circuit group is configured to:
supply a first program permission voltage to bit lines of memory cells, each having a threshold voltage lower than the second sub-verification voltage,
supply a second program permission voltage higher than the first program permission voltage to bit lines of memory cells, each having a threshold voltage higher than the first sub-verification voltage and lower than the target verification voltage,
supply a third program permission voltage higher than the second program permission voltage to bit lines of the fast program memory cells, and
supply a program inhibition voltage higher than the third program permission voltage to bit lines of memory cells, each having a threshold voltage higher than the target verification voltage.