Method and apparatus to reduce a quantity of error detection/correction bits in memory coupled to a data-protected processor port
An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.
1. An interface device configured to interface between a processing device and a memory device, the interface device comprising;
an error correcting code (ECC) encoder, the ECC encoder calculating at least one ECC bit and providing the at least one ECC bit to the processing device based at least in part on data provided by the memory device, the processing device comprising an ECC-based memory interface port, thereby eliminating a need to store the at least one ECC bit in the memory device;
a parity encoder, the parity encoder providing at least one parity bit to the memory device based on data provided by the processing device while ignoring at least one ECC bit provided by said processing device; and
a parity decoder, the parity decoder selectively modifying the at least one ECC bit provided to the processing device based on the data provided by the memory device and at least one parity bit provided by the memory device, the parity decoder inverting a plurality of ECC bits to the processing device in response to the data provided by the memory device and the at least one parity bit provided by the memory device indicating an error associated with the data provided by the memory device.
2. The interface device defined by claim 1 , wherein the processing device does not support a parity-based memory device.
3. The interface device defined by claim 1 , wherein the memory device comprises at least one of a parity-based interface and an interface not requiring any error or parity-based protection.
4. The interface device defined by claim 1 , wherein the ECC encoder is configured to provide a plurality of ECC bits, the parity decoder being configured to selectively modify the plurality of ECC bits provided to the processing device as a function of the data provided by the memory device and the at least one parity bit provided by the memory device.
5. The interface device defined by claim 1 , wherein the processing device comprises the ECC encoder.
6. A method of interfacing between a processing device and a memory device, the method comprising;
calculating at least one error correcting code (ECC) bit and providing the at least one ECC bit to the processing device based at least in part on data provided by the memory device, the processing device comprising an ECC-based memory interface port, thereby eliminating a need to store the at least one ECC bit in the memory device;
providing at least one parity bit to the memory device as a function of data provided by the processing device while ignoring at least one ECC bit provided by said processing device;
selectively modifying the at least one ECC bit provided to the processing device based on the data provided by the memory device and at least one parity bit provided by the memory device; and
inverting a plurality of ECC bits to the processing device in response to the data provided by the memory device and the at least one parity bit provided by the memory device indicating an error associated with the data provided by the memory device.
7. The method defined by claim 6 , wherein the processing device does not support a parity-based memory device.
8. The method defined by claim 6 , wherein the memory device comprises at least one of a parity-based interface and an interface not requiring any error or parity-based protection.
9. The method defined by claim 6 , further comprising;
providing a plurality of ECC bits; and
modifying selectively the plurality of ECC bits provided to the processing device based on the data provided by the memory device and the at least one parity bit provided by the memory device.
10. The method defined by claim 6 , wherein providing at least one ECC bit based at least in part on data provided by the memory device is performed by the processing device.
11. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform a computer process comprising:
calculating at least one error correcting code (ECC) bit based at least in part on data provided by a memory device; and
providing the at least one ECC bit to the processing device, the processing device comprising an ECC-based memory interface port, thereby eliminating a need to store the at least one ECC bit in the memory device;
providing at least one parity bit to the memory device based on data provided by the processing device while ignoring at least one ECC bit provided by said processing device;
selectively modifying the at least one ECC bit provided to the processing device as a function of the data provided by the memory device and at least one parity bit provided by the memory device; and
inverting a plurality of ECC bits to the processing device in response to the data provided by the memory device and the at least one parity bit provided by the memory device indicating an error associated with the data provided by the memory device.
12. The non-transitory computer-readable medium defined by claim 11 , wherein the processing device does not support a parity-based memory device.
13. The non-transitory computer-readable medium defined by claim 11 , wherein the memory device comprises at least one of a parity-based interface and an interface not requiring any error or parity-based protection.
14. The non-transitory computer-readable medium defined by claim 11 , wherein the computer process further comprises;
providing a plurality of ECC bits; and
modifying selectively the plurality of ECC bits to the processing device as a function of the data provided by the memory device and the at least one parity bit provided by the memory device.
15. The non-transitory computer-readable medium defined by claim 11 , wherein providing at least one ECC bit based at least in part on data provided by the memory device is performed by the processing device.