Schottky diode and method of manufacture
A method of manufacturing Schottky diodes in a CMOS process includes forming wells, including first wells ( 16 ) for forming CMOS devices and second wells ( 18 ) for forming Schottky devices. Then, transistors are formed in the first wells, the second wells protected with a protection layer ( 20 ) and suicide contacts ( 40 ) formed to source and drain regions in the first wells. The protection layer is then removed, a Schottky material deposited and etched away except in a contact region in each second well to form a Schottky contact between the Schottky material ( 74 ) and each second well ( 18 ).
1. A method of manufacturing a semiconductor device including a plurality of transistors in a first region and a Schottky device in a second region, the method comprising:
forming a plurality of n-type doped wells and p-type doped wells in the first region and a plurality of n-type doped wells and p-type doped wells in the second region;
depositing a protection layer on the exposed semiconductor of each well in the second region;
forming a silicide on the transistor wells of the first region by depositing a silicidation metal over the surface, annealing to form a silicide of the silicidation metal and removing the silicidation metal leaving the silicide;
removing the protection layer of each well in the second region;
depositing a Schottky material over the surface including exposed semiconductor of each well in the second region; and
etching away the Schottky material except in a contact region in the well or wells in the second region to form a Schottky contact between the Schottky material and the well or wells in the second region.
2. A method according to claim 1 wherein the Schottky material is TiN, TaN or W.
3. A method according to claim 1 wherein the Schottky material is TiN.
4. A method according to claim 1 wherein the step of depositing the Schottky material includes depositing the Schottky material to a predetermined thickness to form a Schottky barrier of corresponding predetermined height.
5. A method according to claim 1 further comprising forming a gate stack between the source and drain regions in wells in the first region to form transistors before the step of depositing a protection layer.
6. A method according to claim 5 further comprising forming spacers around the gate stacks before the step of depositing a protection layer.
7. A method according to claim 5 wherein the transistors formed in the n-type doped wells and p-type doped wells are complementary metal oxide semiconductor transistors.
8. A method according to claim 2 wherein the Schottky material is TiN.
9. A method according to claim 2 wherein the step of depositing the Schottky material includes depositing the Schottky material to a predetermined thickness to form a Schottky barrier of corresponding predetermined height.
10. A method according to claim 3 wherein the step of depositing the Schottky material includes depositing the Schottky material to a predetermined thickness to form a Schottky barrier of corresponding predetermined height.
11. A method according to claim 8 wherein the step of depositing the Schottky material includes depositing the Schottky material to a predetermined thickness to form a Schottky barrier of corresponding predetermined height.
12. A method according to claim 2 further comprising forming a gate stack between the source and drain regions in wells in the first region to form transistors before the step of depositing a protection layer.
13. A method according to claim 3 further comprising forming a gate stack between the source and drain regions in wells in the first region to form transistors before the step of depositing a protection layer.
14. A method according to claim 4 further comprising forming a gate stack between the source and drain regions in wells in the first region to form transistors before the step of depositing a protection layer.
15. A method according to claim 8 further comprising forming a gate stack between the source and drain regions in wells in the first region to form transistors before the step of depositing a protection layer.
16. A method according to claim 6 wherein the transistors formed in the n-type doped wells and p-type doped wells are complementary metal oxide semiconductor transistors.
17. A method according to claim 1 , before depositing the protection layer, further comprising:
implanting p+ type implants in:
the n-type doped wells in the first region to form source and drain regions of some of said transistors; and
the p-type doped wells in the second region to form contact regions of the p-type doped wells in the second region.
18. A method according to claim 1 , before depositing the protection layer, further comprising:
implanting n+ type implants in:
the p-type doped wells in the first region to form source and drain regions of some of said transistors; and
the n-type doped wells in the second region to form contact regions of the n-type doped wells in the second region.