Chip on chip semiconductor device including an underfill layer having a resin containing an amine-based curing agent

1. A semiconductor device, comprising:

a wiring substrate having a wiring layer at least at one principle surface;

a stacked body mounted at the principle surface of the wiring substrate, in which two or more semiconductor chips are stacked and disposed with a predetermined interval and respective semiconductor chips are electrically connected with each other via bumps;

an underfill layer including a resin and filled into gaps between the respective semiconductor chips of the stacked body, the resin containing an amine-based curing agent, and the resin having a glass transition temperature (Tg) of 65° C. or more and 100° C. or less; and

a molding body including a molding resin and covered and formed at outside of the stacked body.

2. The semiconductor device according to claim 1 ,

wherein the stacked body includes a first semiconductor chip disposed in a face-up manner at the principle surface of the wiring substrate, and a second semiconductor chip disposed such that an element circuit surface faces thereto and of which an area of a principle surface is smaller than that of the first semiconductor chip.

3. The semiconductor device according to claim 1 ,

wherein the resin is an epoxy-based resin.

4. The semiconductor device according to claim 1 ,

wherein the underfill layer further includes an inorganic filler in which an average particle size is less than 0.5 μm.

5. The semiconductor device according to claim 4 ,

wherein the inorganic filler is a silica powder.

6. The semiconductor device according to claim 1 ,

wherein the bump is constituted by at least one kind of a metal material selected from Sn based solders such as Sn—Ag solders and Sn—Cu solders, Au, Sn, Cu, Ag, Pd and Ni.

7. The semiconductor device according to claim 1 ,

wherein a diameter of the bump is 5 μm to 50 μm, and a pitch of an array of the bumps is 10 μm to 100 μm.

8. The semiconductor device according to claim 1 ,

wherein a gap between respective semiconductor chips constituting the stacked body is 5 μm to 50 μm.

9. The semiconductor device according to claim 1 ,

wherein thicknesses of the two or more semiconductor chips constituting the stacked body are each 350 μm or less.

10. The semiconductor device according to claim 1 ,

wherein the molding resin has 130° C. to 200° C. of the Tg, 0.8 ppm/° C. to 1.4 ppm/° C. of a thermal expansion coefficient at a temperature of less than the Tg (CTE1), 3.0 ppm/° C. to 4.9 ppm/° C. of a thermal expansion coefficient at a temperature of the Tg or more (CTE2), and 15 GPa to 30 GPa of a bending elasticity modulus.

11. The semiconductor device according to claim 1 ,

wherein the molding resin is an epoxy-based resin.

12. The semiconductor device according to claim 1 ,

wherein a side edge surface of the molding body is vertically formed relative to the principle surface of the wiring substrate.

13. The semiconductor device according to claim 1 ,

wherein the stacked body has a structure in which two or more semiconductor chips in which areas of principle surfaces are approximately identical are disposed with a predetermined interval with each other, and connected via the bumps.

14. The semiconductor device according to claim 13 ,

wherein thicknesses of the two or more semiconductor chips constituting the stacked body are each 50 μm or less.

15. The semiconductor device according to claim 5 ,

wherein the underfill layer includes 50 mass % or more of the silica powder.

16. The semiconductor device according to claim 2 ,

wherein the wiring substrate has a connection terminal of gold, and the first semiconductor chip and the connection terminal is connected via a second bump.