Semiconductor device and method of fabricating same
A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
1. A method of manufacturing a semiconductor device, the method comprising:
forming isolation regions in a substrate, the substrate comprising a core region and an I/O region;
forming a resistor over the isolation region and a first gate stack in the I/O region, wherein the first gate stack does not include a high-k gate dielectric;
recessing the substrate in the core region to form a first recess;
growing a strained silicon channel in the first recess;
forming a second gate stack over the strained silicon channel, wherein the second gate stack comprises a high-k gate dielectric;
recessing a portion of the strained silicon channel to form a second recess; and
growing a source region in the second recess, the source region having a raised profile.
2. The method of claim 1 , further comprising forming spacers adjacent to the resistor, the first gate stack, and the second gate stack.
3. The method of claim 1 , wherein the growing the strained silicon channel further comprises:
growing a layer of silicon-germanium; and
growing a layer of silicon.
4. The method of claim 1 , wherein the growing the source region further comprises:
growing a layer of silicon-germanium; and
growing a layer of silicon-carbon.
5. The method of claim 1 , further comprising:
performing an LDD ion implantation into the I/O region; and
annealing the semiconductor device subsequent to the LDD ion implantation.
6. The method of claim 1 , further comprising forming a masking layer over the first gate stack and the resistor prior to recessing the substrate.
7. The method of claim 6 , wherein the masking layer is silicon nitride.
8. A method of manufacturing a semiconductor device, the method comprising:
forming a resistor over an isolation region, the isolation region extending into a substrate;
forming a first gate dielectric in an I/O region of the substrate, wherein the first gate dielectric does not include a high-k material;
removing a portion of the substrate in a core region of the substrate;
epitaxially growing a strained silicon channel in the core region after the removing the portion of the substrate;
forming a second gate dielectric over the strained silicon channel, wherein the second gate dielectric comprises a high-k material;
removing a portion of the strained silicon channel after the forming the second gate dielectric; and
epitaxially growing a source/drain region in the core region after the removing the portion of the strained silicon channel, the source/drain region exhibiting a raised profile.
9. The method of claim 8 , further comprising forming spacers adjacent to the resistor, the first gate dielectric, and the second gate dielectric.
10. The method of claim 8 , wherein the growing the strained silicon channel further comprises:
growing silicon-germanium; and
growing silicon.
11. The method of claim 8 , wherein the growing the source region further comprises:
growing silicon-germanium; and
growing silicon-carbon.
12. The method of claim 8 , further comprising:
performing an LDD ion implantation into the substrate within the I/O region; and
performing an anneal subsequent to the LDD ion implantation.
13. The method of claim 8 , further comprising forming a masking layer over the first gate dielectric and the resistor prior to recessing the substrate.
14. The method of claim 13 , wherein the masking layer is silicon nitride.
15. A method of manufacturing a semiconductor device, the method comprising:
separating a substrate into a core region and an I/O region with isolation regions;
forming a first gate dielectric over the substrate in the I/O region, wherein the first gate dielectric is not a high-k dielectric material;
depositing a conductive material over the I/O region, the core region, and the isolation regions;
patterning the conductive material to form a first gate electrode over the first gate dielectric and a resistor over one of the isolation regions;
recessing the substrate in the core region and growing a strained silicon channel in the core region;
depositing a second gate dielectric over the strained silicon channel, the second gate dielectric comprising a high-k material; and
recessing the strained silicon channel after the depositing the second gate dielectric and growing source/drain regions to a point higher than a bottom surface of the second gate dielectric.
16. The method of claim 15 , further comprising forming spacers adjacent to the resistor and the first gate electrode.
17. The method of claim 15 , wherein the growing the strained silicon channel further comprises:
growing a layer of silicon-germanium; and
growing a layer of silicon.
18. The method of claim 15 , wherein the growing the source/drain regions further comprises:
growing a layer of silicon-germanium; and
growing a layer of silicon-carbon.
19. The method of claim 15 , further comprising:
performing an LDD ion implantation into the I/O region; and
annealing the semiconductor device subsequent to the LDD ion implantation.
20. The method of claim 15 , further comprising forming a masking layer over the first gate electrode and the resistor prior to recessing the substrate.