3-D nonvolatile memory device and method of manufacturing the same, and memory system including the 3-D nonvolatile memory device
A three-dimensional (3-D) nonvolatile memory device includes vertical channel layers protruded from a substrate, interlayer insulating layers and memory cells, which are alternately stacked along the vertical channel layers, and select transistors including planar channel layers, each contacted with at least one of the vertical channel layers and being parallel to the substrate, and gate insulating layers formed over the planar channel layers.
1. A three-dimensional (3-D) nonvolatile memory device, comprising:
a plurality of vertical channel layers protruded from a substrate;
a plurality of interlayer insulating layers and a plurality of memory cells, which are alternately stacked along the plurality of vertical channel layers; and
a plurality of select transistors comprising a plurality of planar channel layers, each contacted with at least one of the vertical channel layers and being parallel to the substrate, and gate insulating layers formed over the plurality of planar channel layers.
2. The 3-D nonvolatile memory device of claim 1 , wherein each of the select transistors further comprises a select line formed over the gate insulating layer and extended in one direction.
3. The 3-D nonvolatile memory device of claim 2 , further comprising spacers formed on sidewalls of the select lines and configured to have an etch selectivity to the interlayer insulating layers.
4. The 3-D nonvolatile memory device of claim 1 , further comprising a junction formed within the planar channel layer between the select transistors.
5. The 3-D nonvolatile memory device of claim 4 , further comprising a source line or a bit line coupled to the junction.
6. The 3-D nonvolatile memory device of claim 1 , further comprising a plurality of sub-select lines formed between the plurality of memory cells and the select transistor, configured to surround the plurality of vertical channel layers, and extended in parallel in one direction.
7. The 3-D nonvolatile memory device of claim 1 , further comprising:
a pipe gate formed under the plurality of memory cells with the interlayer insulating layers interposed between the pipe gate and the memory cells; and
pipe channel layers filled within the pipe gate and each configured to couple a pair of the vertical channel layers.
8. The 3-D nonvolatile memory device of claim 7 , wherein the planar channel layers are coupled to vertical channel layers adjacent to each other and coupled to the respective pipe channel layers, from among the plurality of vertical channel layers, in common.
9. The 3-D nonvolatile memory device of claim 1 , wherein the memory cells comprise:
word lines configured to surround the vertical channel layer and disposed over the substrate; and
a tunnel insulating layer, a charge trap layer, and a charge blocking layer interposed between the vertical channel layer and the word lines.
10. The 3-D nonvolatile memory device of claim 1 , wherein the memory cells comprises:
a tunnel insulating layer configured to surround the vertical channel layer;
a floating gate configured to surround the tunnel insulating layer;
word lines configured to surround the vertical channel layer and stacked with a floating gate interposed between the memory cells and the word lines; and
a charge blocking layer interposed between the word lines and the floating gate.
11. The 3-D nonvolatile memory device of claim 1 , further comprising:
a gap-fill insulating layer filled within the vertical channel layer and configured to have a lower height than the vertical channel layer; and
a doped polysilicon layer formed over the gap-fill insulating layer, filled within the vertical channel layer, and configured to come in contact with the planar channel layer.
12. A memory system, comprising:
a three-dimensional (3-D) nonvolatile memory device configured to comprise a plurality of vertical channel layers protruded from a substrate, a plurality of interlayer insulating layers and a plurality of memory cells alternately stacked along the plurality of vertical channel layers, and a plurality of select transistors configured to comprise a plurality of planar channel layers, each contacted with at least one of the vertical channel layers and being parallel to the substrate, and gate insulating layers formed over the plurality of planar channel layers; and
a memory controller configured to control the 3-D nonvolatile memory device.