Memory power tokens
Techniques are described for controlling availability of memory. As memory write operations are processed, the contents of memory targeted by the write operations are read and compared to the data to be written. The availability of the memory for subsequent write operations is controlled based on the outcomes of the comparing. How many concurrent write operations are being executed may vary according to the comparing. In one implementation, a pool of tokens is maintained based on the comparing. The tokens represent units of power. When write operations require more power, for example when they will alter the values of more cells in PCM memory, they draw (and eventually return) more tokens. The token pool can act as a memory-availability mechanism in that tokens must be obtained for a write operation to be executed. When and how many tokens are reserved or recycled can vary according to implementation.
1. A method of controlling write operations in a phase change material (PCM) memory, the method comprising:
for a first write operation directed to a part of the PCM memory, determining difference information corresponding to a number of bit differences between data requested to be stored by the first write operation and data in the part of the PCM memory; and
controlling timing of performing a second write operation based on the determined difference information corresponding to the number of bit differences between the data in the part of the PCM memory and the data requested to be stored by the first write operation.
2. A method according to claim 1 , wherein the controlling is performed by maintaining write information that reflects an amount of the PCM memory determined to be subject to physical modification by write operations.
3. A method according to claim 2 , wherein the write information comprises a fluctuating number, and the controlling comprises checking the current value of the fluctuating number to determine whether or when to allow execution of the second write operation.
4. A method according to claim 3 , wherein the fluctuating number is increased or decreased according to the difference information.
5. A method according to claim 3 , further comprising adding to or subtracting from the fluctuating number an amount corresponding or proportional to the number of bit differences.
6. A method according to claim 1 , wherein the difference information is determined by obtaining a count of cells having values determined to differ from values to be written by the first write operation.
7. A storage device comprising:
a memory storing stored data;
a logic component that when executing receives incoming write operations to write data to the storage device, temporarily stores the write operations before implementation thereof, and controls timing of implementation of the write operations according to determinations of individual amounts of bits to be physically updated by the respective write operations.
8. A storage device according to claim 7 , wherein as more data is determined to be physically updated by the write operations delay of the write operations is increased.
9. A storage device according to claim 8 , wherein as less data is determined to be physically updated by the write operations delay of the write operations is increased.
10. A storage device according to claim 7 , wherein a write operation comprises a word to be written, and wherein a determination of an individual amount of bits to be physically updated by the write operation is made by comparing bits of the word with bits of a corresponding part of the PCM memory that corresponds to the write operation.
11. An apparatus to control write operations for a phase change material (PCM) memory, the apparatus comprising:
a bit comparing circuit that, when the apparatus is in operation, for a first write operation directed to a part of the PCM memory, determines difference information corresponding to a number of bit differences between data requested to be stored by the first write operation and data in the part of the PCM memory; and
a controlling circuit that, when the apparatus is in operation, controls timing of performing a second write operation based on the determined difference information corresponding to the number of bit differences between the data in the part of the PCM memory and the data requested to be stored by the first write operation.