Power OK distribution for multi-voltage chips
A method and apparatus for powering up an integrated circuit (IC). An IC includes a plurality of power domains each coupled to receive power from one of a plurality of power sources. Each power domain includes a power-sensing unit. A power-sensing unit in a first one of the plurality of power domains is coupled to receive a first power ok signal from an upstream power domain, and is configured to assert a second power ok signal to be provided to a second power domain. A power-sensing unit in the second power domain is coupled to detect the presence of voltage in the first power domain, and to receive the first power ok signal. When the power-sensing unit in the second power domain has both sensed the presence of power in the first power domain and received the second power ok signal, a third power ok signal is asserted.
1. An apparatus comprising:
an integrated circuit having a plurality of power domains implemented thereon, wherein each of the plurality of power domains is responsive to receiving power from a respective one of a plurality of power supplies; and
a plurality of serially-coupled power-sensing units including a first power-sensing unit and a second power-sensing unit implemented on the integrated circuit, wherein the first power-sensing unit is coupled to receive a first signal indicating that at least a first one of the plurality of power domains is receiving power from its respective one of the plurality of power supplies, wherein the first power-sensing unit is implemented in and is configured to sense power in a second one of the plurality of power domains, and wherein the first power-sensing unit is configured to assert a second signal in response to the first signal and sensing power in the second one of the plurality of power domains, wherein the second power-sensing unit is coupled to receive the second signal.
2. The apparatus as recited in claim 1 , wherein the first power domain is responsive to receiving power from a first one of the plurality of power supplies and wherein the second power domain is responsive to receiving power from a second one of the plurality of power supplies.
3. The apparatus as recited in claim 1 , further comprising a third one of the plurality of power domains, wherein the third one of the plurality of power domains includes the second power-sensing unit, wherein the second power-sensing unit is configured to sense power in the third one of the plurality of power domains and assert a third signal responsive to receiving the second signal and sensing power in the third one of the plurality of power domains.
4. The apparatus as recited in claim 1 , wherein two or more of the plurality of power domains are each associated with corresponding ones of the plurality of power-sensing units.
5. The apparatus as recited in claim 1 , wherein the integrated circuit includes is configured to be held in a reset state until one of the plurality of power-sensing units asserts a signal indicating that power is stable in each of the plurality of power domains.
6. The apparatus as recited in claim 1 , wherein each of the plurality of power-sensing units is identical.
7. The apparatus as recited in claim 1 , wherein the first power-sensing unit includes a level shifting circuit, wherein the level shifting circuit is configured to assert the second signal.
8. The apparatus as recited in claim 7 , wherein the level shifting circuit is configured to delay the assertion of the second signal.
9. The apparatus as recited in claim 1 , wherein the first one of the plurality of power domains includes circuitry configured to operate at a first supply voltage and wherein the second one of the plurality of power domains includes circuitry configured to operate at a second supply voltage different from the first supply voltage.
10. An apparatus comprising:
a first power domain implemented on an integrated circuit and configured to receive power from a first power source;
a second power domain implemented on the integrated circuit and configured to receive power from a second power source; and
a plurality of serially-coupled power sensing units including a first power-sensing unit implemented in the second power domain of the integrated circuit and a second power-sensing unit implemented in a third power domain of the integrated circuit, wherein the first power-sensing unit is coupled to receive a first signal indicating that at least one of the first and second power sources is providing power to its respective power domain, where the first power-sensing unit is configured to sense power in at least one of the first and second power domains, and wherein the first power-sensing unit is configured to assert a second signal in response to the first signal and sensing power in at least one of the first or second power domains, wherein the second power-sensing unit is coupled to receive the second signal.
11. The apparatus as recited in claim 10 , wherein the first power-sensing unit is configured to receive power from the second power source.
12. The apparatus as recited in claim 10 , wherein the second power-sensing unit is configured to sense power in the third power domain, and wherein the second power-sensing unit is configured to assert a third signal responsive to receiving the second signal and sensing power in the third power domain.
13. The apparatus as recited in claim 10 , wherein the first power-sensing unit includes a level shifting circuit configured to assert the second signal.
14. The apparatus as recited in claim 13 , wherein the level shifting circuit is configured to delay assertion of the second signal.
15. The apparatus as recited in claim 10 , and wherein the apparatus is configured to be held in a reset state until one of the plurality of power-sensing units asserts a signal indicating that each of the plurality of power domains is receiving power.
16. A method comprising:
receiving power at a plurality of power domains implemented on an integrated circuit;
asserting a first signal in response to at least a first one of the plurality of power domains receiving power; and
asserting a second signal in response to a first power-sensing unit detecting assertion of the first signal and power in a second one of the plurality of power domains, the first power-sensing unit being one of a plurality of serially-coupled power sensing units;
wherein the first and second signals are asserted by the first power-sensing unit, wherein the first power sensing unit is implemented in the second one of the plurality of power domains, wherein a second power-sensing unit of the plurality of serially-coupled power-sensing units is coupled to receive the second signal.
17. The method as recited in claim 16 , wherein the second power-sensing unit of the plurality of serially-coupled power-sensing units asserts a third signal in response to detecting assertion of the second signal and power in a third one of the plurality of power domains.
18. The method as recited in claim 16 , further comprising maintaining the integrated circuit in a reset state until one of a plurality of serially-coupled power-sensing units asserts a signal indicating that power is stable in each of the plurality of power domains.
19. The method as recited in claim 16 , further comprising delaying assertion of the second signal.